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我有一些相当大的设计,我能够在FPGA上实现,但从设计总结来看,我无法弄清楚FPGA架构上剩余多少可用空间。 设备利用率如下。 我可以理解基元,特征利用,i / o利用等利用率。 但对于FPGA架构本身,哪个指标可以最好地估算FPGA上用完/空闲的空间量? 是使用切片regs,切片luts使用或否。 切片被占用了? 此外,在利用百分比时,最好是开始拆分FPGA代码并将其分配到2个FPGA(主从类型的布局)上吗? 感谢致敬, 祖宾库马尔。 切片逻辑利用率:切片寄存器数量:32,640中的20,413 62%用作触发器的数量:20,381用作锁存器的数量:32 切片LUT的数量:32,640中的22,036 67%用作逻辑的数字:32,640中的20,868 63%仅使用O6输出的数字:15,718仅使用O5输出的数字:1,596使用O5和O6的数字:3,554 用作存储器的数字:12,480中的161个1%用作移位寄存器的数字:161仅使用O6输出的数字:160仅使用O5输出的数字:1用作独占路由的数字:1,007路由数量:3,000个 65,280 4%仅使用O6输出的数字:1,742仅使用O5输出的数字:402使用O5和O6的数字:856 切片逻辑分布:占用切片数:8,160中的7,558 92%使用的LUT触发器对的数量:27,130带未使用的触发器的数量:27,130中的6,717 24%带有未使用的LUT的数量:27,130中的5,094 18%数量 完全使用的LUT-FF对:27,130中的15,319 56%独特控制集的数量:731控制集限制丢失的切片寄存器站点数量:32,640中的1,342 4% IO利用率:保税IOB数量:480个中的361个75% 特定功能利用率:BlockRAM / FIFO数量:132个中的120个90%仅使用BlockRAM的数量:120 使用的总原语:使用的36k BlockRAM数量:107使用的18k BlockRAM数量:25使用的总内存(KB):4,752中的4,302 90%BUFG / BUFGCTRL数量:32个中的6个18%用作BUFG的数量:6个数字 DCM_ADVs:12个中的2个16%DSP48E数量:288个中的77个26% 以上来自于谷歌翻译 以下为原文 Hi, I had some rather large designs which I was able to imlpement on the FPGA, but from the design summary, I was not able ot figure out how much free space is left on the FPGA fabric. The device utilization is below. I can understand utilization such as that of primitives, feature utilization, i/o utilization. But For the FPGA fabric itself, which metric gives the best estimate of the amount of space used up/free on the FPGA? Is it slice regs used, slice luts used or no. of slices occupied? Also, at what %utilization, is it a good idea to start breaking up the FPGA code and distributing it on 2 FPGAs (master-slave type of arrangement)? Thanks and regards, Zubin Kumar. Slice Logic Utilization: Number of Slice Registers: 20,413 out of 32,640 62% Number used as Flip Flops: 20,381 Number used as Latches: 32 Number of Slice LUTs: 22,036 out of 32,640 67% Number used as logic: 20,868 out of 32,640 63% Number using O6 output only: 15,718 Number using O5 output only: 1,596 Number using O5 and O6: 3,554 Number used as Memory: 161 out of 12,480 1% Number used as Shift Register: 161 Number using O6 output only: 160 Number using O5 output only: 1 Number used as exclusive route-thru: 1,007 Number of route-thrus: 3,000 out of 65,280 4% Number using O6 output only: 1,742 Number using O5 output only: 402 Number using O5 and O6: 856 Slice Logic Distribution: Number of occupied Slices: 7,558 out of 8,160 92% Number of LUT Flip Flop pairs used: 27,130 Number with an unused Flip Flop: 6,717 out of 27,130 24% Number with an unused LUT: 5,094 out of 27,130 18% Number of fully used LUT-FF pairs: 15,319 out of 27,130 56% Number of unique control sets: 731 Number of slice register sites lost to control set restrictions: 1,342 out of 32,640 4% IO Utilization: Number of bonded IOBs: 361 out of 480 75% Specific Feature Utilization: Number of BlockRAM/FIFO: 120 out of 132 90% Number using BlockRAM only: 120 Total primitives used: Number of 36k BlockRAM used: 107 Number of 18k BlockRAM used: 25 Total Memory used (KB): 4,302 out of 4,752 90% Number of BUFG/BUFGCTRLs: 6 out of 32 18% Number used as BUFGs: 6 Number of DCM_ADVs: 2 out of 12 16% Number of DSP48Es: 77 out of 288 26% |
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这与“电路板使用”无关。
如果您不知道来自IC的电路板......您使用62%的寄存器,67%的LUT,90%的RAM,26%的DSP,而不是其他。 因此,BlockRAM的使用对你来说非常重要。如果不了解你正在使用的家庭,就不能说更多。 ------------------------------------------“如果它不起作用 模拟,它不会在板上工作。“ 以上来自于谷歌翻译 以下为原文 This is NOTHING to do with "board usage". If you don't know a board from an IC... You are using 62% of the registers, 67% of the LUTs, 90% of the RAM, 26% of the DSPs, and not much else. BlockRAM usage is therefore the important figure for you. Can't say much more without knowing wahat family you are using. ------------------------------------------ "If it don't work in simulation, it won't work on the board." |
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我使用的FPGA是Xilinx Virtex5 XC5VSX50T。
以上来自于谷歌翻译 以下为原文 The FPGA I am using is Xilinx Virtex5 XC5VSX50T. |
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虽然Block RAM的百分比最高,但使用100%的Block RAM是完全合理的
资源(鉴于您不希望扩展设计)。 然而,使用100%是非常困难的 结构LUT或寄存器没有遇到问题。 如你所见,虽然规模较大 两者中只有67%,你至少部分使用92%的切片。 当你开始添加更多 逻辑上,更多的切片将被充分利用,因此更多的切片将具有一些不相关的切片 逻辑挤在一起。 这最终会使布局和布线非常困难,尤其是如果 你需要满足激进的时间限制。 大型Virtex 5中67%的LUT或触发器 可能是开始考虑划分设计的好地方。 请注意,在较小的 FPGA,这个百分比可能更大,因为你没有那么大的可能路由 较小面料的距离。 非常低密度的FPGA可以使用非常接近100%。 Virtex 5 SX50T可能在70-75%LUT或寄存器之间 在你需要花费大量时间进行时序收敛之前。 - Gabor - Gabor 以上来自于谷歌翻译 以下为原文 While block RAM is the highest percentage, it is perfectly reasonable to use 100% of block RAM resources (given you don't expect to expand the design). However it is very hard to use 100% of the fabric LUTs or registers without running into problems. As you can see, although the larger of the two is only 67%, you are at least partially using 92% of the slices. As you start to add more logic, more of the slices will be fully utilized, and more slices will thus have some unrelated logic packed together. This eventually makes placement and routing very hard, especially if you need to meet aggressive timing constraints. 67% of LUTs or flip-flops in a large Virtex 5 is probably a good place to start thinking about partitioning the design. Note that in a smaller FPGA, this percentage may be larger because you don't have as large a possible routing distance in a smaller fabric. Very low density FPGA's can be used very close to 100%. The Virtex 5 SX50T is probably good up to somewhere between 70-75% LUTs or registers before you need to spend a lot of time on timing closure. -- Gabor -- Gabor |
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