请问有哪位大神知道am5728 evm从EMMC的启动流程吗？

你好
       我板子的串口启动u-boot可以正常读写nand，
       如果是从nand启动，烧写SPL,和u-boot.img之后，上电之后没有任何相应，
下面是nand布局（请问nand布局是在设备树中吗）：
partition@0 [/* 256KB */
label = "NAND.SPL";
reg = <0x00000000 0x00040000>;
];
partition@1 [/* 256KB */
label = "NAND.SPL.backup1";
reg = <0x00040000 0x00040000>;
];
partition@2 [/* 256KB */
label = "NAND.SPL.backup2";
reg = <0x00080000 0x00040000>;
];
partition@3 [/* 256KB */
label = "NAND.SPL.backup3";
reg = <0x000C0000 0x00040000>;
];
partition@4 [/* 512KB */
label = "NAND.u-boot-spl-os";
reg = <0x00100000 0x00080000>;
];
partition@5 [/* 2MB */
label = "NAND.u-boot";
reg = <0x00180000 0x00200000>;
];
partition@6 [/* 256KB */
label = "NAND.u-boot-env";
reg = <0x00380000 0x00040000>;
];
partition@7 [/* 256KB */
label = "NAND.u-boot-env.backup1";
reg = <0x003C0000 0x00040000>;
];
partition@8 [/* 8MB */
label = "NAND.kernel";
reg = <0x00400000 0x00800000>;
];
partition@9 [/* 500MB */
label = "NAND.file-system";
reg = <0x00C00000 0x1F400000>;
];
请问在nand启动的流程
感激不尽

看看启动模式对不对，需要通过JTAG读取BOOTCFG寄存器

你好，
             我的仿真器使用的是00IC-XDS100V3，ccs版本是6.2.0
  
[Start: Texas Instruments XDS100v3 USB Debug Probe_0]
Execute the command:
%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]

-----[Print the board config pathname(s)]------------------------------------
C:UsersadminAppDataLocalTEXASI~1CCS
tiBrdDattestBoard.dat
-----[Print the reset-command software log-file]-----------------------------
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesu***v3.dll'.
The library build date was 'Jul 27 2016'.
The library build time was '18:31:37'.
The library package version is '6.0.407.3'.
The library component version is '35.35.0.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
-----[Print the reset-command hardware log-file]-----------------------------
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).
-----[The log-file for the JTAG TCLK output generated from the PLL]----------
Test Size Coord MHz Flag Result Description
~~~~ ~~~~ ~~~~~~~ ~~~~~~~~ ~~~~ ~~~~~~~~~~~ ~~~~~~~~~~~~~~~~~~~
1 64 - 01 00 500.0kHz O good value measure path length
2 64 + 00 00 1.000MHz [O] good value apply explicit tclk
There is no hardware for measuring the JTAG TCLK frequency.
In the scan-path tests:
The test length was 2048 bits.
The JTAG IR length was 6 bits.
The JTAG DR length was 1 bits.
The IR/DR scan-path tests used 2 frequencies.
The IR/DR scan-path tests used 500.0kHz as the initial frequency.
The IR/DR scan-path tests used 1.000MHz as the highest frequency.
The IR/DR scan-path tests used 1.000MHz as the final frequency.
-----[Measure the source and frequency of the final JTAG TCLKR input]--------
There is no hardware for measuring the JTAG TCLK frequency.
-----[Perform the standard path-length test on the JTAG IR and DR]-----------
This path-length test uses blocks of 64 32-bit words.
The test for the JTAG IR instruction path-length failed.
The JTAG IR instruction scan-path is stuck-at-ones.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 32 bits.
-----[Perform the Integrity scan-test on the JTAG IR]------------------------
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Test 1 Word 0: scanned out 0xFFFFFFFF and scanned in 0xFFFFFFC1.
Scan tests: 1, skipped: 0, failed: 1
Do a test using 0x00000000.
Test 2 Word 0: scanned out 0x00000000 and scanned in 0x0000003F.
Scan tests: 2, skipped: 0, failed: 2
Do a test using 0xFE03E0E2.
Test 3 Word 0: scanned out 0xFE03E0E2 and scanned in 0x80F83880.
Test 3 Word 1: scanned out 0xFE03E0E2 and scanned in 0x80F838BF.
Test 3 Word 2: scanned out 0xFE03E0E2 and scanned in 0x80F838BF.
Test 3 Word 3: scanned out 0xFE03E0E2 and scanned in 0x80F838BF.
Test 3 Word 4: scanned out 0xFE03E0E2 and scanned in 0x80F838BF.
Test 3 Word 5: scanned out 0xFE03E0E2 and scanned in 0x80F838BF.
The details of the first 8 errors have been provided.
The utility will now report only the count of failed tests.
Scan tests: 3, skipped: 0, failed: 3
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 4
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 5
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 6
Some of the values were corrupted - 67.2 percent.
The JTAG IR Integrity scan-test has failed.
-----[Perform the Integrity scan-test on the JTAG DR]------------------------
This test will use blocks of 64 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Test 3 Word 0: scanned out 0xFE03E0E2 and scanned in 0xFC07C1C5.
Test 3 Word 1: scanned out 0xFE03E0E2 and scanned in 0xFC07C1C5.
Test 3 Word 2: scanned out 0xFE03E0E2 and scanned in 0xFC07C1C5.
Test 3 Word 3: scanned out 0xFE03E0E2 and scanned in 0xFC07C1C5.
Test 3 Word 4: scanned out 0xFE03E0E2 and scanned in 0xFC07C1C5.
Test 3 Word 5: scanned out 0xFE03E0E2 and scanned in 0xFC07C1C5.
Test 3 Word 6: scanned out 0xFE03E0E2 and scanned in 0xFC07C1C5.
Test 3 Word 7: scanned out 0xFE03E0E2 and scanned in 0xFC07C1C5.
The details of the first 8 errors have been provided.
The utility will now report only the count of failed tests.
Scan tests: 3, skipped: 0, failed: 1
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 2
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 3
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 4
Some of the values were corrupted - 66.7 percent.
The JTAG DR Integrity scan-test has failed.
[End: Texas Instruments XDS100v3 USB Debug Probe_0]

我的电脑无法发新贴，只能在这里请教了！
AM335X 是否可以将nand配置在CS0使用0x10000000地址256M宽度！然后配置访问FPGA的CS1~CS3配置在0x08000000这边的地址！
//CS1
HWREG(GPMC_CONFIG_REGS + 0xA8) = 0x00000000;
HWREG(GPMC_CONFIG_REGS + 0x90) = 0x28001200;
HWREG(GPMC_CONFIG_REGS + 0x94) = 0x000f1001;
HWREG(GPMC_CONFIG_REGS + 0x98) = 0x22060411;
HWREG(GPMC_CONFIG_REGS + 0x9C) = 0x0e097018;
HWREG(GPMC_CONFIG_REGS + 0xA0) = 0x000d1010;
HWREG(GPMC_CONFIG_REGS + 0xA4) = 0x09070000;
HWREG(GPMC_CONFIG_REGS + 0xA8) = 0x00000F48;

//CS2
HWREG(GPMC_CONFIG_REGS + 0xD8) = 0x00000000;
HWREG(GPMC_CONFIG_REGS + 0xC0) = 0x28001200;
HWREG(GPMC_CONFIG_REGS + 0xC4) = 0x000f1001;
HWREG(GPMC_CONFIG_REGS + 0xC8) = 0x22060411;
HWREG(GPMC_CONFIG_REGS + 0xCC) = 0x0e097018;
HWREG(GPMC_CONFIG_REGS + 0xD0) = 0x000d1010;
HWREG(GPMC_CONFIG_REGS + 0xD4) = 0x09070000;
HWREG(GPMC_CONFIG_REGS + 0xD8) = 0x00000F49;

//CS3
HWREG(GPMC_CONFIG_REGS + 0x108) = 0x00000000;
HWREG(GPMC_CONFIG_REGS + 0xF0) = 0x28001200;
HWREG(GPMC_CONFIG_REGS + 0xF4) = 0x000f1001;
HWREG(GPMC_CONFIG_REGS + 0xF8) = 0x22060411;
HWREG(GPMC_CONFIG_REGS + 0xFC) = 0x0e097018;
HWREG(GPMC_CONFIG_REGS + 0x100) = 0x000d1010;
HWREG(GPMC_CONFIG_REGS + 0x104) = 0x09070000;
HWREG(GPMC_CONFIG_REGS + 0x108) = 0x00000F4a;
我配置完这个后，访问0x08000000~0x0affffff中任意个地址都出现地址异常！直接就死掉！
跟踪后都是跳到了
LDR PC,Reset_Addr ; Reset
LDR PC,Undefined_Addr ; Undefined instructions
LDR PC,SWI_Addr ; Software interrupt (SWI/SVC)
LDR PC,Prefetch_Addr ; Prefetch abort
LDR PC,Abort_Addr ; Data abort
LDR PC,Unused_Addr ; RESERVED
LDR PC,IRQ_Addr ; IRQ
LDR PC,FIQ_Addr ; FIQ
中的LDR PC,Abort_Addr ; Data abort这里？
请求解答：：：：是不能这样配置还是我什么地方有问题？？？？？？？

已经解决，MMU地址配置错了！！！

问题解决了，是nandR/B引脚的电阻接错了，将上拉电阻换为10K电阻之后，启动正常了