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通过VHDL设计一个简单信号发生器,有一路输出outp。仿真时,始终没有输出结果,outp一直为低,查看其中状态的变化,发现状态却是一直变化的,请问这是由于什么造成的。
--------------------------- --------信号发生器--------- --------------------------- library ieee; use ieee.std_logic_1164.all; --------------------------- entity pro_signal is port( clk:in std_logic; outp:out bit ); end pro_signal; ---------------------------- architecture pro_signal of pro_signal is signal out1,out2:bit; type state is (one,two,three); signal pr_state1,nx_state1:state; signal pr_state2,nx_state2:state; begin ----------down section--------- ----------machine #1------------ process(clk) begin if(clk'event and clk='1')then pr_state1<=nx_state1; end if; end process; ----------machine #2------------ process(clk) begin if(clk'event and clk='0')then pr_state2<=nx_state2; end if; end process; -------------up section----------- ------------machine #1------------ process(pr_state1) begin case pr_state1 is when one => out1<='1'; nx_state1<=two; when two => out1<='1'; nx_state1<=three; when three => out1<='0'; nx_state1<=one; end case; end process; ------------machine #2------------ process(pr_state2) begin case pr_state2 is when one => out1<='0'; nx_state2<=two; when two => out1<='1'; nx_state2<=three; when three => out1<='1'; nx_state2<=one; end case; end process; outp<=out1 and out2; end pro_signal; |
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没有帮顶的吗?
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代码错误,已解决!
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