Quartus中的一些warning及解决方法

【非原创声明】做FPGA久了就会发现其实我们不能只局限于解决ERROR，综合过程中的有些Warning其实也是必须修掉的重要提示，不能忽视。我从网上摘了一些别人总结的经验，再自己补充一些整理在下面：

1. Warning: VHDL Process Statement warning at random.vhd(18): signal reset is in statement, but is not in sensitivity list

【提示】没把singal放到process（）中。

2.Warning: Found pins ing as undefined clocks and/or memory enables
Info: Assuming node CLK is an undefined clock

【提示】是说设计中没有对时钟进行约束。【解决】在assignment/timing anlaysis setting/inidividual clock中设置

3. Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "clk_gen:clk_gen1|clk_incr" as buffer
Info: Detected ripple clock "clk_gen:clk_gen1|clk_scan" as buffer

【提示】设计中出现门控时钟问题，最好修掉，时钟分析会更容易通过，系统更稳。如果是必须的，可以忽略此提示。

4. Warning: VHDL Process Statement warning at ledmux.vhd(15): signal or variable "dataout" may not be assigned a new in every possible path through the Process Statement. Signal or variable "dataout" holds its previous in every path with no new assignment, which may create a combinational loop in the current design.

【提示】电路设计里面出现了组合逻辑信号反馈的一个闭环。这样没有经过寄存器的反馈会造成电路很不稳定，很容易出现毛刺。建议修改。

5. Warning: No clock transition on "counter_bcd7:counter_counter_clk|q_sig[3]" register

【提示】寄存器没有接时钟。

6. Warning: Reduced register "counter_bcd7:counter_counter_clk|q_sig[3]" with stuck clock port to stuck GND

【提示】寄存器没有赋值，软件自动将输入接GND。

7. Warning: Circuit may not operate. Detected 1 non-operational path(s) clocked by clock "class[1]" with clock skew larger than data delay. See Compilation Report for details.

【提示】时序分析中出现的warning，提示clock skew太大，严重影响到时序，建议查出原因坚决修掉。具体原因要参考report。

8.  Warning: Ignored node in vector source file. Can't find corresponding node name "class_sig[2]" in design.

【提示】所提示的信号没有连接或定义到高层。

9. Warning: Found clock high time violation at 1000.0 ns on register "|fcounter|lpm_counter:temp_rtl_0|dffs[4]"

【提示】仿真中出现的，提示时序很紧，适当降低主时钟频率再仿真。

10. Warning: Compiler packed, optimized or synthesized away node "temp[19]". Ignored vector source file node.

【提示】信号没有最终使用，被软件自动优化去掉了。

11. Warning: Design contains 2 input pin(s) that do not drive logic

Warning: No output dependent on input pin "clk"
Warning: No output dependent on input pin "sign"

【提示】两个信号在电路中未被使用，没有驱动任何电路，最终也会被优化掉。

12. Warning: Ignored node in vector source file. Can't find corresponding node name "over" in design.

【提示】在源文件中找不到对应的节点“over”。

13.Warning: Synthesized away the following node(s):

【提示】以下节点都被综合优化掉。

14.Warning: Output pins are stuck at VCC or GND

        Warning (13410): Pin "USB_SLOE" is stuck at VCC

【提示】输出信号连接到固定值，如果是实际情况可以忽略，不是的话就去看看原因吧。

15.Warning: Some pins have incomplete I/O assignments. Refer to the I/O Assignment Warnings report for details

【提示】top层有些管脚没有绑定到FPGA pin上面。仔细找找吧。

16.Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled

【提示】PLL的相位没有设置或默认为0.确实不需设置的时候可以忽略。

17.Warning：“xxxx” used but never defined...

【提示】XXX信号已经使用但是没有定义，这个一定要定义的哦。

18.Warning：“xxxx” defined but never used...
【提示】XXX信号已经定义但是没有使用，这个可以忽略。但是要问问自己问什么定义呢？

太好了。。。。谢谢

Warning (10631): VHDL Process Statement warning at kongzhi.vhd(26): inferring latch(es) for signal or variable "nzkz", which holds its previous value in one or more paths through the process

这是什么意思啊？怎么解决啊？