1、通过QuartusII中的设置实现
完成下列两个设置即可实现:
"Remove redundant logic cells" , must be "off"
"Ignore LCELL buffers", must be "off"
You will find these 2 set tings in the settings ->Analysis&Synthesis -> more settings
2、通过在HDL中添加综合属性来实现
1)、下面是一个例子,首先代码中没有添加综合属性
library IEEE;
- use IEEE.std_logic_1164.all;
- use IEEE.std_logic_arith.all;
- use IEEE.std_logic_unsigned.all;
entity LcellTest is
-
- port (
- clk : in std_logic;
- din : in std_logic;
- dout : out std_logic
- );
- end LcellTest;
-
- architecture rtl of LcellTest is
- signal reg1,reg2,reg3: std_logic;
component lcell
- port (
- a_in : in std_logic;
- a_out : out std_logic
- );
- end component;
-
- begin
-
- u1:lcell
- port map (a_in => din, a_out => reg1);
- u2:lcell
- port map (a_in => reg1, a_out => reg2);
- u3:lcell
- port map (a_in => reg2, a_out => reg3);
- u4:lcell
- port map (a_in => reg3, a_out => dout);
-
- end rtl;
复制代码
上面没有添加综合属性代码编译后,通过Tchnology Map View(post-fitting)查看如下:
可以看到代码中例化的所有lcell都被优化掉了。
2)、将代码修改(即添加相应的综合属性见紫红色段)如下:
library IEEE;
- use IEEE.std_logic_1164.all;
- use IEEE.std_logic_arith.all;
- use IEEE.std_logic_unsigned.all;
entity LcellTest is
-
- port (
- clk : in std_logic;
- din : in std_logic;
- dout : out std_logic
- );
- end LcellTest;
-
- architecture rtl of LcellTest is
- signal reg1,reg2,reg3: std_logic;
- attribute keep : boolean;
- attribute keep of reg1,reg2,reg3 : signal is true;
component lcell
- port (
- a_in : in std_logic;
- a_out : out std_logic
- );
- end component;
-
- begin
-
- u1:lcell
- port map (a_in => din, a_out => reg1);
- u2:lcell
- port map (a_in => reg1, a_out => reg2);
- u3:lcell
- port map (a_in => reg2, a_out => reg3);
- u4:lcell
- port map (a_in => reg3, a_out => dout);
-
- end rtl;
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上面添加综合属性后代码全编译查看Technology Map View(post-fitting)结果为:
从上图可以看到保留了3个lcell。
3)、假如既将第一种方法中的选项“off”掉,同时在代码中对reg1、reg2以及reg3添加keep属性,则编译结果如下:
4)、这里补充只“off”掉方法一的选项,而不添加keep属性,则上面代码编译结果为:
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好东西 感谢分享!
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