关于28035的ADC的中断的疑问的解决办法？

28035的ADC的采样完成之后生成的EOCX，ADC的配置如下：
EALLOW;
AdcRegs.ADCCTL1.bit.INTPULSEPOS = 1; //ADCINT1 trips after AdcResults latch
AdcRegs.INTSEL1N2.bit.INT1E = 1; //Enabled ADCINT1
AdcRegs.INTSEL1N2.bit.INT1CONT = 0; //Disable ADCINT1 Continuous mode
AdcRegs.INTSEL1N2.bit.INT1SEL = 1; //setup EOC1 to trigger ADCINT1 to fire
AdcRegs.ADCSOC0CTL.bit.CHSEL = 0; //set SOC0 channel select to ADCINA0
AdcRegs.ADCSOC1CTL.bit.CHSEL = 2; //set SOC1 channel select to ADCINA2
AdcRegs.ADCSOC2CTL.bit.CHSEL = 4; //set SOC2 channel select to ADCINA4
AdcRegs.ADCSOC3CTL.bit.CHSEL = 6; //set SOC3 channel select to ADCINA6
AdcRegs.ADCSOC0CTL.bit.TRIGSEL = 1; //set SOC0 start trigger on TIME0, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC1CTL.bit.TRIGSEL = 1; //set SOC1 start trigger on TIME0, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC2CTL.bit.TRIGSEL = 1; //set SOC2 start trigger on TIME0, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC3CTL.bit.TRIGSEL = 1; //set SOC3 start trigger on TIME0, due to round-robin SOC0 converts first then SOC1
AdcRegs.ADCSOC0CTL.bit.ACQPS = 6; //set SOC0 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC1CTL.bit.ACQPS = 6; //set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC2CTL.bit.ACQPS = 6; //set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
AdcRegs.ADCSOC3CTL.bit.ACQPS = 6; //set SOC1 S/H Window to 7 ADC Clock Cycles, (6 ACQPS plus 1)
EDIS;
由以上的配置可知，中断产生的配置是由EOC1产生的，但是有序列配置可知，总共转换的通道数为四个 也就是说为0 1 2 3 当通道1完成数据的生成，生成了E0C1，此时进入中断，这时在中断里面不应该可以的数据就是通道0和1的吗，为什么也可以接受到2和3顺序通道转换的数据呢？？？？