请问谁能给我这个电阻的阻值在PSOC 5开漏输出时提供？

数据表并没有明确地说出那个数字。我能想到的最好的是输入电流输入。对于正常的GPIO，这是2 NA。对于SiO输入，当输入电压大于Vddsio时，其14NA或10μA。从这些数字可以计算电阻（它们用3V输入电压指定）。



     以下为原文
  The data sheet does not explicitely tell that number. The best I can come up with is the input current into the inputs. For a normal GPIO, this is 2 nA. For a SIO inputs its 14nA, or 10µA when the input voltage is greater than Vddsio. From these numbers you can calculate the resistance (they are specified with a 3V input voltage).

亲爱的RLI，
什么是SIO输入。请说明它是否与漏极输入相同。



     以下为原文
  Dear Rli ,
    What is an SIO input. Please clarify whether it is same as an open drain input

SIO是一种特殊的输入引脚。它允许启用一些特殊特性（例如更高的输出驱动器，能够处理高于电源电压的输入电压）。正常和SIO引脚都可以设置为打开漏极。
也许我建议您阅读PSoC5LP数据表和PoS5LP的体系结构参考手册（TRM），解释了不同PIN类型的所有细节。



     以下为原文
  SIO is a special kind of input pin. It allows for some special features to be enabled (e.g. higher output drive, ability to handle input voltages higher than supply voltage). Both normal and SIO pins can be set to open drain.
    Maybe I suggest you read the PSOC5LP data sheet, and the architecture reference manual (TRM) for the PSoC5LP, there all the details about the different pin types is explained.

亲爱的HLI，
谢谢你的澄清。因此，我可以把高阻抗状态下的电阻值设为3V/10NA。＝300兆欧？



     以下为原文
   dear hli ,
              Thanks for the clarification. so can I take the resistance in the high impeadance state to be 3V/10nA. = 300 Meg ohms?

2 NA是房间温度，最大，而不是生产测试。
像这样的阻抗，10兆赫和更高，非常受
板布局，污染物，表面处理……然后你有交流问题，
如C耦合到引脚在高Z状态…
如果你进一步描述你需要什么加载，电路问题，等等，也许我们可以帮助你进一步。
问候，Dana。



     以下为原文
  The 2 nA is room temp only, max, and not production tested.
     
    Impedances like this, 10's of megohms and higher, are very subject to
    board layout, contaminants, surface treatment........Then you have AC issues,
    eg C coupling to pins in Hi Z state........
     
    If you describe further what you need for loading, circuit issues, etc..,  maybe we can help you further.
     
    Regards, Dana.

附上一些有用的参考文献。
问候，Dana。
设计-毫安-电路-低泄漏-部分-邮编
3.6兆字节



     以下为原文
  Some useful references, attached.
     
    Regards, Dana.

•   Design-femtoampere-circuits-with-low-leakage-part-one.zip 3.6 MB  
  
  

但是对于PSoC，2NA的数字仍然是真实的。它独立于你正在做的板8-是的，得到低于2nA泄漏电流将是棘手的）。



     以下为原文
  But the 2nA figure is still true for the PSoC. Its independent of what you are doing with the board 8and yes, getting to below 2nA leakage current there will be tricky).

2的NA是在室温下的最大值，在生产中没有测试。但是
泄漏只是试图达到这些水平的问题的一部分。
Z的设计。孤立PSOC泄漏部分
设计问题。路由和附加部件和温度A大
HZ设计中的因素。一切都很重要。
问候，Dana。



     以下为原文
  The 2 nA is a max value at room temp, not tested in production. But
    that leakage is only part of the problem trying to achieve these levels
    of Z in a design. Taken in isolation the leakages of PSOC only part
    of the design issues. Routing and attached parts and temp a big
    factor in Hi Z designs. Everything is important.
     
    Regards, Dana.

朋友，
我做了以下测试与PSOC引脚在开式排水下拉模式。
首先，在高阻模式下放置开路漏极引脚，然后使用外部电流源输入恒定电流。
我把一个10纳米安培电流注入引脚。
我测量了那个针上的电压。所测量的电压相对于VSSA/GND精确为1 V。
因此，从这些观察中，我得出结论，在高阻模式下由开式漏极引脚提供的沟道电阻约为10兆欧。
请提供意见，修改/建议，如果有的话



     以下为原文
   friends,
                    I did the following test with the PSoC pin in open drain pull down mode. 
    First I put the open drain pin in high impeadance mode then I used an external current source to input a constant current.
    I sourced a current of 10 nano amperes into the pin.
    I measured the voltage developed on that pin. The measured voltage was exactly 1 V with respect to VSSA/GND.
    So from these observations I conclude that the channel resistance offered by an open drain pin in the high impeadance mode is around 10 Megohms.
    Please provide comments, corrections / suggestions if any

你考虑过测量设备的阻抗吗？对于这样的高阻抗情况，测量工具阻抗会影响读数。



     以下为原文
  Have you consider the impedance of your measuring equipment. For such a high impedance situation, the measuring tools impedance would affect the reading. 

你必须小心这里测量高Z通常意味着
您使用具有线性滤波器抑制功能的DVM。你也可以
测量电流源的顺应极限吗？
就你所测量的，销上的泄漏是F（t，共），
二次V效应……并且不是生产测试（由于稳定时间）
采取测量，因此测试时间）。它是一个布局泄漏的组合，
二极管泄漏，MOSFET泄漏，ESD保护电路……
所以，如果你真的需要非常高的Z保护，你可能不得不和警卫在一起。
什么是为你好Z驱动你的需要，Z .....目标？
问候，Dana。



     以下为原文
  You have to be careful here as measurement of high Z generally means
    you use a DVM with line filter rejection capabilities. Also could you have
    been measuring the complient limit of your current source ?
     
    In so far as what you measure, the leakage on a pin, is a f( T, contaimanents,
    second order V effects....) and is not production tested (due to settling time
    to take a measurement hence test time). It is a combination of layout leakage,
    diode leakage, MOSFET leakage, ESD protection circuits......
     
    So if you truly need very high Z guarenteed you may have to do that off chip with guards.
     
    What is driving your need for the hi Z, target for Z.....?
     
    Regards, Dana.

达纳，
我想用高Z来保持电容器上的电荷。每当我想要电容器放电时，我会把电容器端子拉到地上。



     以下为原文
   dana, 
             I want to use the High Z for holding charges on a capacitor. Whenever I want to discharge the capacitor I would pull down the capacitor terminal to ground.

那么，你需要像创造者一样的样本和保持组件吗？
我们谈论的是什么电容，它应该保持多长时间？你肯定电容器的自放电电流低于PSoC漏电流吗？



     以下为原文
  So you need something like the Sample&Hold-Component available in Creator?
    What capacitance are we talking about, and how long should it hold its charge? Are you sure the self-discharge current of the capacitor is lower than the PSoC leakage current?

正如HLI指出的，你必须为你的设计回答几个问题。
1）贮存时间
2）获取时间
3）精度
4）分辨率
5）下垂
当然，您可以一直这样做，用Delsig测量引脚电压，并将其存储在EEPROM中。
几乎不受限制，不关心温度、电容器质量、老化、辅助泄漏……
电压与VDAC或如果更多的分辨率需要PWM，然后LPF。
除非我们知道更多关于目标、你想要完成的事情，否则我们无法帮助你。
问候，Dana。



     以下为原文
  As HLI points out you have to answer for your design several questions -
    1) Storage time
    2) Acquistion time
    3) Accuracy
    4) Resolution
    5) Droop
     
    Of course you can always do this digitally, measure the pin voltage with DelSig, and store it in EEPROM
    almost indefinitely with no concerns for temp, capacitor quality, aging, ancillary leakages......You can reporduce the
    voltage with VDAC or if more resolution needed PWM followed by LPF.
     
    Until we know more about goals, what you are trying to accomplish, we cannot assist you furthur.
     
    Regards, Dana.

Yuiu可能会发现这是有用的
HTTP://wwwDaseHealSoviv.COM/Fiels/NealAl/HTM/NSC0883.HTM Bob Pease
还有谷歌“SAMPPLKE HORD设计”，很多点击，AUROIGG设备，TI……
问候，Dana。



     以下为原文
  Yoiu might find this useful -
     
        
              
    http://www.datasheetarchive.com/files/national/htm/nsc03883.htm     Bob Pease
     
    Also google "samplke hold design", many hits, analoig devices, TI.........
     
     
    Regards, Dana.

亲爱的丹娜& HLI，
我只想在电容器上保持大约200MV的电压（2微微法拉第，所以毫微微库仑电荷）大约10微秒。我们可以合理地假定电容器的泄漏为零安培。只是在最坏的情况下，包括所有非理想的引脚电阻的值就满足了我的要求。



     以下为原文
   Dear danaa & Hli ,
    I just want to hold a voltage of say around 200mV on the capacitor(2 pico faarads, so femto coulombs of charge) for around 10 micro seconds. We can fairly assume the leakage of the capacitor to be zero amps. just the value of the pin resistance in the worst case including all non idealities would suffice for my requirement.

因此，您可以在Grave:HTTP://wwwyCysP.COM/？RID＝56758



     以下为原文
  So you can use the Sample&Hold component in Creator: http://www.cypress.com/?rID=56758

“非理想”的问题在于它们有这么多。PCB上的污垢、焊锡残留物、指纹、印刷电路板本身——它们都漏电流。
只需测量10MHH8，我想它只是你的仪表的输入阻抗）：2PF，10MOHM和10μs的电压降大约为40%（如果我计算正确）。如果你计算的300摩尔是正确的，那么下降大约是1.7%。也许你可以做一些测量，看看下降实际上是多少？



     以下为原文
  The problem with the 'non-idealities' is that there are so many of them. Dirt on the PCB, solder residue, fingerprints, the PCB itself - they all leak current.
    Just taking your measurement of 10MOhm 8which Ithink is just the input impedance of your meter): 2pF, 10MOhm and 10µS result in a voltage drop of about 40% (if I calculate right). If the 300MOhm you calculated are right, then the drop is about 1.7%. Maybe you can run some measurements and see how much the drop actually is?

我只想在电容器上保持大约200MV的电压（2微微法拉第，所以毫微微库仑电荷）大约10微秒。我们可以合理地假定电容器的泄漏为零安培。只是在最坏的情况下，包括所有非理想的引脚电阻的值就满足了我的要求。
一个2的PF上限对于S/H应用来说是非常小的，只是杂散的C变化影响结果。q＝c x v，i＝c dv/dt。
你必须瞄准一些可接受的下垂、分辨率和计算。说我们想要
10位精度（我将使用1000作为一个整数），允许下垂1 LSB，因此允许下垂
DV＝200紫外，
所以我们有I＝（2 pF x 200 UV）/10 US＝40 pA。这完全依赖于不现实的当前值，
热会把它吹到黑洞里去。
不仅当充电帽时，还具有寄生栅C的电荷馈送。
通过某种类型的多路复用器/开关。和其他开关耦合的设计。
Dana，想想吧。



     以下为原文
  I just want to hold a voltage of say around 200mV on the capacitor(2 pico faarads, so femto coulombs of charge) for around 10 micro seconds. We can fairly assume the leakage of the capacitor to be zero amps. just the value of the pin resistance in the worst case including all non idealities would suffice for my requirement.
     
    A 2 pF cap is pretty small for a S/H application, just stray C changes affect outcome. Q = C x V, I = C dV/dT.
    You have to target some acceptable droop, resolution, and do the calculations. Say we wanted
    10 bit accuray (I will use 1000 as a round number), allowed droop of 1 l***, so droop allowed
    dV = 200 uV,
     
    So we have I = ( 2 pf x 200 uV ) / 10 uS = ~ 40 pA. Thats totaly unrealistsic current value to rely on,
    and hot will blow that away into a black hole.
     
    Not only that you have the charge feed thru of parasitic gate C when you are charging cap
    thru a mux/switch of some sort. And other switching coupling in the design.
     
    Food for thought, Dana.