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[问答] 尝试编程spartan3s50an fpga错误
135 FPGA mode 引脚
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我正在尝试编程spartan3s50an FPGA并且它给了我这个错误。
这些是我设置的配置
VSEL​​引脚0的值:VSEL引脚1的0值:VSEL引脚的0值:MODE引脚的0值M0:MODE引脚的1值M1:MODE引脚的1值M2:CFG_RDY的1值(INIT_B):来自Done引脚的1DONEIN输入:1
“配置数据下载到FPGA不成功.DONE没有变高,请检查配置设置和spi模式设置。”
请帮我解决这个问题

以上来自于谷歌翻译


以下为原文

I am trying to program spartan3s50an fpga and it is giving me this error.
These ae the configuration that i have set
value of VSEL pin 0                               :         0
value of VSEL pin 1                               :         0
value of VSEL pin 2                               :         0
value of MODE pin M0                          :         1
value of MODE pin M1                          :         1
value of MODE pin M2                          :         0
value of CFG_RDY (INIT_B)               :         1
DONEIN input from Done Pin            :         1

"Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and spi mode settings."

Please help me regarding this problem
0
2019-7-29 10:14:45   评论 分享淘帖 邀请回答

相关问题

12个回答
您应该上拉变量选择引脚VS [2:0]。
来自Spartan 3 Generatuion用户指南
UG332:
-  Gabor

以上来自于谷歌翻译


以下为原文

You should pull up the Variant select pins VS[2:0].  From the Spartan 3 Generatuion User's guide
ug332:
 

-- Gabor
2019-7-29 10:28:51 评论

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来自UG332 v1.6
当iMPACT 9.1i配置Spartan-3AN FPGA时,它首先对内部SPI Flash PROM进行编程。
完成此配置后,将触发重新启动,并且FPGA将从内部SPI PROM进行自我配置。
当重启被触发时,模式引脚M [2:0]被采样。
要使配置成功完成,FPGA模式选择引脚必须设置为M [2:0] =,这是内部主SPI模式。
如果从iMPACT进行配置,并且模式引脚设置为JTAG模式M [2:0] =,则FPGA的配置将无法完成。
要完成FPGA的配置,您只需将模式引脚更改为内部主SPI模式,并将PROG引脚脉冲触发配置,或通过iMPACT重新配置。
在iMPACT 9.2i及更高版本中,您可以选择直接通过JTAG模式配置FPGA,也可以编程内部SPI PROM,然后通过内部主SPI模式进行配置。
如果您使用IMPACT 9.2i或更高版本,则下载到FPGA或内部SPI闪存应该已经成功。
如果您使用的是早期版本的IMPACT,则MODE和VSEL引脚对于成功至关重要,并且(正如Gabor指出的那样)VSEL引脚设置不正确。
Spartan-3AN系列在VSEL引脚上有内部上拉电阻,您无需将任何其他内容连接到VSEL引脚(除非配置后VSEL引脚是用户IO引脚)。
当然,即使使用JTAG,也必须取消激活PROG_B(必须为高电平)才能使FPGA配置或下载成功。
您使用的是什么版本的IMPACT?
IMPACT是否为FPGA返回正确的ID代码?
IMPACT会发现内部SPI闪存吗?
- 鲍勃埃尔金德
签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。
阅读手册或用户指南。
你读过手册了吗?
你能找到手册吗?2。
搜索论坛(并搜索网页)以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题,开始新的主题!5。
学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息(请与网页,数据表链接).7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章,那么我一无所获。

以上来自于谷歌翻译


以下为原文

From UG332 v1.6
When iMPACT 9.1i configures the Spartan-3AN FPGAs, it first programs the internal SPI Flash PROM. After this configuration is complete, a reboot is triggered and the FPGA configures itself from the internal SPI PROM. When the reboot is triggered, the mode pins M[2:0] are sampled. For the configuration to complete successfully, the FPGA mode select pins must be set to M[2:0] = <0:1:1>, which is the Internal Master SPI mode.


If you are configuring from iMPACT and your mode pins are set to JTAG mode M[2:0] = <1:0:1>, configuration of the FPGA will not complete. To finish configuration of the FPGA, you can simply change the mode pins to Internal Master SPI mode and pulse the PROG pin to trigger configuration, or reconfigure through iMPACT.


In iMPACT 9.2i and later, you have the option to either configure the FPGA directly through JTAG mode or to program the Internal SPI PROM and then configure through Internal Master SPI mode.
If you are using IMPACT 9.2i or later, your download to the FPGA or internal SPI flash memory should have been successful.
 
If you are using an earlier version of IMPACT, your MODE and VSEL pins are critical for success, and (as Gabor points out) the VSEL pins are set incorrectly.  Spartan-3AN family has internal pulllups on the VSEL pins, you need not connect anything else to the VSEL pins (unless the VSEL pins are user IO pins after configuration).
 
And of course, PROG_B must be de-asserted (must be HIGH) for FPGA configuration or download to be successful, even when using JTAG.
 
What version of IMPACT are you using?  Does IMPACT return the correct ID code for the FPGA?  Does IMPACT discover the internal SPI flash memory?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.
2019-7-29 10:38:20 评论

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我一直在追逐这个问题超过一年。
似乎在文档UG332,DS557和其他几个文档中有一些不成文或难以找到的内容。
我已经读了这么多。
我有两个硬件设计都使用XC3S50AN-TQG144
设计1)一旦FPGA启动并运行,M0,M1M2都被指定为输入。
如果通过三态缓冲器将它们提供给程序并运行功能,则使它们能够上拉和下拉,并在电路板PU脉冲(100mS)期间强制进入三态。
这允许1k上拉和下拉电阻器在该初始时段期间定义它们的状态。
两个跳线将电阻连接到+ 3.3v或gnd,具体取决于我是要编程还是运行。
正常运行时M2 = 0,M1 = 1,M0 = 1
对于JTAG编程,M2 = 1,M1 = 0,M0 = 1。
VS2,VS1,VS0使用相同的硬件系统,但正常读取的1k电阻总是连接1,0,1。
PUC_B通过1K电阻永久连接到3.3V。
INIT_B和PROG_B通过1k电阻拉至3.3v。
DONE通过1k和LED串联连接到3.3v,以便我可以看到它是否保持低电平。
结果:我总是可以对闪存和FPGA进行编程(第一个影响选项),但总是失败并且DONE为低(完成LED低)但是它已经成功编程,我每次都可以100%校正校验和来验证它。
它运作良好。
唯一的烦恼是在影响报告失败之前的长时间超时。
设计2)
与设计1相同,但是一旦FPGA启动并运行,M2,M1,M0,VS2,VS1,VS0引脚都将用作输出。
它们具有相同的上拉/下降布置,并具有相同的跳线布置。
为了防止这些引脚驱动的电路以错误的方向拉动它,我使用非反相cmos门来缓冲实际负载。
这是一个更简单的解决方案。
结果:在程序模式下:与设计1相同 - “完成失败”但编程实际上成功了。
在运行模式下:我可以100%成功编程,并且完成了很高的!!
如果我不需要跳线 - 我可以在运行状态下硬线M2,M1,M0。
上述两种情况都是使用Impact 10.1和12.4发生的,除了12.4在失败之前似乎有一个令人讨厌的超时!
我实际上可以在超时期间再次打开电源并获得“成功”,因为这样可以让DONE变高。
Xilinx用于测试此功能的确切电路是什么?
有模仿的电路吗?
你可以说我的设计2是解决方案,但为什么呢?
为什么它在运行模式下编程?
听起来我实际上并没有“触及现场”

以上来自于谷歌翻译


以下为原文

I have been chasing this problem for over a year. It seems that there is something unwritten or difficult to find in the documentation UG332, DS557 and several others. I have read so much on this.
 
I have two hardware designs both using XC3S50AN-TQG144
 
Design 1) M0,M1M2 are all designated as inputs once the FPGA is up and running. To enable them to be pulled up and down for the program and run functions if feed them through a tri-state buffer which is forced in to tri-state during the board PU pulse (100mS). That allows the 1 k pull up and down resistors to define their states during that initial period. Two jumpers connect the resistors to +3.3v or gnd depending on whether I want to program or run.
M2=0, M1=1,M0=1 for normal running
M2=1 ,M1=0 , M0=1 for JTAG programming.
The same hardware system is used for VS2,VS1,VS0 but the 1 k resistors connect always 1,0,1 for the normal read.
PUC_B is connected permanently to 3.3V via 1K resistor..
INIT_B and PROG_B are pulled to 3.3v via 1k resistors.
DONE is connected to 3.3v via a 1k and LED in series so that I can see if it stays low.
Result: I can always program the flash and FPGA (first Impact option) but is always fails with DONE low (done led low) however it has successfully programmed and I can read the checksum 100% correct every time to verify it. It functions fine. The only irritation is the long timeout before impact reports that it has failed.
 
Design 2)
That same as design 1 but M2,M1,M0,VS2,VS1,VS0 pins are all used as outputs once the FPGA is up and running.
They have the same arrangement of pull-up/downs with the same arrangement of jumpers. To prevent the circuit that those pins drive from pulling them in the wrong direction I use non-inverting cmos gates to buffer the actual loads.
It is a simpler solution.
Result:  In program mode: the same as design 1 - "done failed to go high" but programming actually succeeded.
In run mode: I can program 100% successfully and done does go high!! If fact I don't need the jumpers - I can hard wire M2,M1,M0 in the run state.
 
Both of the above situations occur using Impact 10.1 and 12.4 except that 12.4 seems to have an annoyingly longer timeout before fail!  I can actually power off then on again during that timeout and get a "succeed" because that lets DONE go high).
 
 
What exact circuit to Xilinx use for testing this functionality?
Is there a circuit to emulate?
You could say that my design 2 is the solution but why? and why does it program in the run mode? It sounds like I have not actually  "touched the spot"
 
 
2019-7-29 10:53:49 评论

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正如在本主题中已经提到的那样,你应该将VS和M引脚设置为“运行模式”
在冲击完成加载后,FPGA要求从闪存加载自身
闪光。
注意,M引脚不需要设置为JTAG进行编程。
JTAG
无论模式如何都会有效。
“JTAG模式”的目的是防止
当您没有其他配置源时,FPGA会尝试自我配置。

可能会注意到较新的设备不再具有此模式,因为任何“奴隶”
模式实现了同样的目的。
对于DONE引脚问题,与上拉串联的LED可能就足够了
保持DONE低于逻辑阈值。
我建议并联一个电阻
您现在使用LED +电阻(从DONE引脚直接连接到Vcc)。
交替
如果您在此DONE行上只有一个设备,则可以更改您的bigten设置
“Drive DONE high”或“Use internal DONE pipe”强制将DONE引脚拉高
没有上拉或使用内部DONE信号而不是等待
把自己钉在高处。
重要的是要注意除非内部信号,否则DONE是双向引脚
用来。
它在多FPGA系统中的目的是允许所有芯片退出
同时配置。
-  Gabor
-  Gabor

以上来自于谷歌翻译


以下为原文

As already noted in this thread, you should have VS and M pins set for "run mode" in
order for the FPGA to load itself from the flash after impact has completed loading
the flash.  Note that the M pins do not need to be set to JTAG for programming.  JTAG
will work regardless of the mode.  The purpose of the "JTAG mode" is to prevent the
FPGA from trying to self-configure when you have no other configuration source.  You
may note that newer devices no longer have this mode, since any of the "slave"
modes accomplish the same purpose.
 
As to the DONE pin problem, an LED in series with the pullup may be enough to
keep DONE below the logic threshold.  I would suggest adding a resistor in parallel
with the LED + resistor you have now (from DONE pin directly to Vcc).  Alternately
if you only have one device on this DONE line, you can change your bigten settings
to "Drive DONE high" or "Use internal DONE pipe" to either force the DONE pin high
without a pullup or to use the internal DONE signal rather than waiting for the
pin itself to go high.
 
It's important to note that DONE is a bidirectional pin unless the internal signal
is used.  Its purpose in a multi-FPGA system is to allow all chips to exit
configuration at the same time.
 
-- Gabor
-- Gabor
2019-7-29 11:13:29 评论

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在加电时进入“运行”模式从来没有问题。
知道M引脚不需要设置为JTAG进行编程当然是有启发性的。
我很想知道哪个文件来自哪里有其他宝石的信息。
到目前为止,我显然已经错过了它。
我对此的主要参考是UG332。
完成问题不会很高。
我已经桥接LED,只留下从DONE引脚到Vcc的470欧姆,仍然是同样的问题。
我独立设置“Drive DONE high”然后“Use internal DONE pipe”。
既没有修好。
我去年试过了。
奇怪的是,大多数JTAG编程操作的DONE都很高。
它只是低到与Impact对话报告“编程已成功完成”并保持低位一致。
然后,Impact等待22秒(Impact 10.1)并报告失败。
随后的校验和测试表明它已编程好。
这几乎就像DONE已经颠倒了逻辑!
我附上了Impact对话框的剪辑。
影响dialog.txt 11 KB

以上来自于谷歌翻译


以下为原文

There is never a problem with getting in to the "run" mode at power-up.
It is certainly enlightening to know that the M pins need not be set to JTAG for programming. I would be interested to know which document that is from in case there are some other gems of information there. I have obviously missed it so far. My main reference for this has been UG332 .
 
Problem with DONE not going high.
I have bridged the LED leaving only the 470 ohms from the DONE pin to Vcc and still the same problem.
I independently set "Drive DONE high" then  "Use internal DONE pipe" . Neither fixed it. I had tried them last year.
The strange thing is that DONE is high for most of the JTAG programming operation. It only goes low to coincide with the Impact dialog reporting "programming completed successfully" and stays low. Impact then waits for 22 seconds (Impact 10.1) and reports a failure. A subsequent checksum test shows that it has programmed OK. It is almost as if DONE has inverted logic!
I have attached a clip of the the Impact dialog.
            impact dialog.txt ‏11 KB
2019-7-29 11:30:23 评论

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知道M引脚不需要设置为JTAG进行编程当然是有启发性的。
我很想知道哪个文件来自哪里有其他宝石的信息。
从UG332开始,第9章的第一行:
Spartan®-3系列FPGA具有专用的四线IEEE 1149.1 / 1532 JTAG端口,无论模式引脚设置如何,只要FPGA上电,该端口始终可用。
要通过JTAG对FPGA进行编程,或通过JTAG间接编程SPI闪存,允许任何模式引脚设置。
当FPGA在JTAG以外的某些模式下进行配置时,必须正确设置模式引脚。
- 鲍勃埃尔金德
签名:新手的自述文件在这里:http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结:1。
阅读手册或用户指南。
你读过手册了吗?
你能找到手册吗?2。
搜索论坛(并搜索网页)以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题,开始新的主题!5。
学生:复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息(请与网页,数据表链接).7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章,那么我一无所获。

以上来自于谷歌翻译


以下为原文

It is certainly enlightening to know that the M pins need not be set to JTAG for programming. I would be interested to know which document that is from in case there are some other gems of information there.
 
From UG332, first lines of chapter 9:
Spartan®-3 generation FPGAs have a dedicated four-wire IEEE 1149.1/1532 JTAG port that is always available any time the FPGA is powered and regardless of the mode pin settings.
 
To program the FPGA via JTAG, or to program the SPI flash memory indirectly via JTAG, any setting of the mode pins are permissible.  When it comes time for the FPGA to configure in some mode other than JTAG, then the mode pins must be set correctly.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.
2019-7-29 11:38:42 评论

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谢谢Gabor和Bob。
我非常感谢你的帮助。
主持人 - 我不确定你想说的是什么:我从“封面到封面!”中读过UG332。
我没有看到第9章的第一行意味着您可以随时使用JTAG进行编程。
它只是sys“可用”。
它并没有说芯片会编程。
有几个地方不这样做。
UG332是一个大型文档,有很多地方可能令人困惑。
推断是我是某种白痴。
40年来,我一直在成功设计电子设备和系统及软件。
令人遗憾的是,该线程现在看起来正在远离真正的“完成”问题,在编程结束时不会很高,这似乎是许多人经历过的问题。

以上来自于谷歌翻译


以下为原文

Thanks Gabor and Bob. I am really grateful for your assistance.
 
Moderator - I am not sure what you are trying to say:  I had read UG332 from "cover to cover!". I had not seen the first lines of chapter 9 to mean that you can program with the JTAG at any time. It just sys "available". It doesn't say that the chip will program. There are several places where it suggest otherwise. UG332 is a large document and there are many places where it can be confusing. The inference is that I am some sort of idiot. I have been designing electronic equipment and systems and software successfully  for 40 years.
 
It is sad that the thread now appears to be heading away from the real problem of "DONE" not going high at the end of programming which seems to be a problem that many have experienced.
 
2019-7-29 11:58:17 评论

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奇怪的是,大多数JTAG编程操作的DONE都很高。
它只是低到与Impact对话报告“编程已成功完成”并保持低位一致。
然后,Impact等待22秒(Impact 10.1)并报告失败。
随后的校验和测试表明它已编程好。
这几乎就像DONE已经颠倒了逻辑!
不,这实际上向您展示了一些重要的东西。
为了编程附加的闪存设备
(在Spartan 3AN的情况下,“内部”闪存是一个独立的芯片),Impact首先下载一个比特流
使用JTAG模式直接连接到FPGA。
该比特流包含允许的“SPI访问核心”
使用JTAG接口通过Spartan 3AN连接到附加SPI闪存的影响。
完成了
当这个“SPI接入核心”比特流成功加载时保持高电平,并保持高电平
闪存程序和验证程序。
最后,Impact强制执行FPGA重新编程循环
通过将PROG_B拉低(内部使用JTAG边界扫描模式)然后再拉高。
此时
为了FPGA,必须为“内部SPI配置”正确设置模式和VS引脚
从闪存加载自己。
如果您的上拉/下拉或主动驱动模式设置未生效
(如果你只使用上电复位来驱动这些引脚就是这种情况)那么FPGA就不会
以正确的配置模式启动。
题:
在通过Impact对闪存进行编程之后,如果您使电路板循环,FPGA是否可以正常启动?
如果是这种情况,那么您至少知道加载到闪存中的配置文件是
正确。
否则,您可能会遇到闪存文件准备问题。
鲍勃的帖子上的一句话(重新:“主持人”):
鲍勃的名字下面的一切都是他的标准签名文件,旨在帮助新手获得
更多来自这些论坛。
这些都不是专门针对你的。
问候,
的Gabor
-  Gabor

以上来自于谷歌翻译


以下为原文

The strange thing is that DONE is high for most of the JTAG programming operation. It only goes low to coincide with the Impact dialog reporting "programming completed successfully" and stays low. Impact then waits for 22 seconds (Impact 10.1) and reports a failure. A subsequent checksum test shows that it has programmed OK. It is almost as if DONE has inverted logic!

No, this is actually showing you something important.  In order to program the attached flash device
(the "internal" flash in the case of Spartan 3AN is a separate die), Impact first downloads a bitstream
directly to the FPGA using JTAG mode.  This bitstream contains the "SPI access core" which allows
Impact to use the JTAG interface to go through the Spartan 3AN to the attached SPI flash.  DONE goes
high when this "SPI access core" bitstream has successfully loaded, and remains high throughout
the flash program and verify procedure.  At the end of this, Impact forces an FPGA re-program cycle
by pulling PROG_B low (internally using JTAG boundary-scan mode) and then high again.  At this time
the mode and VS pins must be correctly set for "internal SPI configuration" in order for the FPGA
to load itself from flash.  If your pull-up / pull-down or active drive mode settings are not in force
(as would be the case if you only use power-on reset to drive these pins) then the FPGA will not
start up in the proper configuration mode.
 
Question:
 
After programming the flash via Impact, does the FPGA boot properly if you powere cycle the board?
 
If this is the case, then you at least know that the configuration file you loaded into the flash is
correct.  Otherwise you could have an issue with the preparation of the file for flash.
 
A word on Bob's post (re: "Moderator"):
 
Everything below Bob's name is his standard signature file intended to help newbies get
more from these forums.  None of it was aimed specifically at you.
 
Regards,
Gabor
-- Gabor
2019-7-29 12:09:31 评论

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的Gabor
谢谢 - 看起来你已经解决了这个问题并解释了很多。
回答你的问题:FPGA在编程和电源循环后总能正常启动。
我做了进一步的测试:我在编程时将电路板/ PU保持为低电平,以便在整个编程过程中M和VS引脚的状态保持为上拉/下拉状态并进行编程。
DONE很高,Impact报告成功!
它解释了一切。
另外,为什么我的实现#2没有问题,因为M和VS引脚被分配为输出,因此不是由外部设备驱动,让上拉/下拉电阻完成它们的工作。
我非常感谢你的帮助。
对于读这个线程的其他人,我会传递我已经学到的结论:如果你要在设计中使用M和VS引脚作为IO,只能将它们用作驱动高阻抗负载的输出(以及添加必要的上拉
/起伏)。

以上来自于谷歌翻译


以下为原文

Gabor
Thanks - it looks like you have solved the problem and explained a lot.
 
Answer to your question: The FPGA always boots properly after programming and a power recycle.
 
I did a further test: I held the board /PU low while programming so that the state of the M and VS pins remained as pulled up/down during the whole programming process and it programmed.  DONE went high and Impact reported success!.
 
It explains everything. Also why I don't have a problem with my implementation #2 because in that the M and VS pins are allocated as outputs therefore are not driven by external devices letting the pull up/down resistors do their work.
 
I am really grateful for your help.
For anyone else reading this thread I would pass on the conclusion that I have learned:  If you are going to use the M and VS pins as IO in a design only use them as outputs driving high impedance loads (as well as adding the necessary pullups/downs).
 
2019-7-29 12:15:51 评论

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很高兴听到你解决了这个问题。
如果您急需引脚并且只剩下VS和M引脚,则另一种可能性:
使用INIT_B信号(最好是拉伸)而不是上电复位来驱动
VS和M引脚来自模式设置而不是它们的主要功能。
FPGA
在INIT_B的上升沿采样VS和M信号(参见“采样”部分
控制引脚“在ug332第12章中。”如果您正在使用具有的上电复位设备
按钮复位的输入,然后您可以将INIT_B信号附加到该设备
最后得到一个适当拉伸的复位信号来驱动模式和VS引脚。
这个
方法应该与Impact和板上电一起使用。
问候,
的Gabor
-  Gabor

以上来自于谷歌翻译


以下为原文

Glad to hear you've solved the problem.
 
One other possibility if you are in dire need of pins and only have VS and M pins left:
 
Use the INIT_B signal (preferably stretched) instead of power-on reset to drive the
VS and M pins from the mode settings instead of their primary functions.  The FPGA
samples the VS and M signals at the rising edge of INIT_B (see the section "Sample
Control Pins" in ug332 chapter 12).  If you're using a power-on reset device that has
an input for a pushbutton reset, then you can attach the INIT_B signal to that device
and end up with a suitably stretched reset signal to drive the mode and VS pins.  This
method should work with Impact as well as on board power-up.
 
Regards,
Gabor
-- Gabor
2019-7-29 12:22:11 评论

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大家好。
但我仍然有问题。
所以我使用的是XC3S50AN-4TQG144I。
问题是我无法将新的编程文件加载到设备。
编程电缆和跳线设置[M2:M0]很好,因为我可以加载前一代设计师创建的MCS文件。
但我需要对设计进行更改(只是将引脚从一个I / O交换到另一个I / O)。
由于这个设计师有一个问题要记住简单的事情(如何编译和获取一个工作的MCS文件)我必须解决这个问题。
我重新编译了项目而没有任何更改,生成了一个新的编程文件(位)并创建了一个新的MCS文件。
当我尝试将其加载到FPGA中时,iMPACT给出了错误“程序失败”。
一个有趣的例子是,新的MCS文件具有不同的大小:旧的有147KByte而新的有124KByte但应该是相同的。
我相信这个问题来自编程文件生成设置,但不知道哪个设置可以帮助我?
我附加了所有设计文件和输出MCS文件(工作一个和一个非工作的新文件)。
先谢谢你了。
伊万。
pulser_1_0__10.mcs 147 KB
pulser_1_0__11.mcs 124 KB
debouncer.vhd 2 KB
LV_PULSER_1_0.vhd 20 KB
tick_gen.vhd 2 KB

以上来自于谷歌翻译


以下为原文

Hello, all.
 
But I still have the problem.
So I am using XC3S50AN-4TQG144I.
The problem is I cannot load the new programming file to device.
Programming cable and jumpers setting [M2:M0] are good as I can load the MCS file created by the previouse designer some time ago. But I need to make changes in design (just to swap the pin from one I/O to another I/O). As this designer has a problem to remember easy things (how to compile and get a working MCS file) I have to resolve this issue.  I recompiled the project without any changes, generated a new programming file (bit) and made a new MCS file. When I try to load it into FPGA, iMPACT gives me error "Program Failed".
One interesting thig is that old a new MCS files have a different size: old has 147KByte and a new has 124KByte but should be the same.
 
I belive this problem come from programing file generation settings but no idea which setting can help me? I attach all design files anf output MCS files (working one and a non-working one-new one).
 
Thank you beforehand.
Ivan.
            pulser_1_0__10.mcs ‏147 KB                pulser_1_0__11.mcs ‏124 KB                debouncer.vhd ‏2 KB                LV_PULSER_1_0.vhd ‏20 KB                tick_gen.vhd ‏2 KB
2019-7-29 12:31:01 评论

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@ ivan.carunas如果你能从下次开始新线程,我会申请。
开始一个新的线程将立即得到关注,并最有可能得到答案。
无论如何,在您生成.mcs并将其用于较新的XC3S50AN-4TQG144I之前,硅制造过程中需要更新文件。
请参阅此通知并遵循AR
http://www.xilinx.com/support/documentation/customer_notices/xcn14003.pdf
http://www.xilinx.com/support/answers/59572.html
我希望一旦你应用补丁,这应该解决你的问题。
-Pratham ------------------------------------------------
----------------------------------------------请注意 - 请
如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用并回复导向的帖子。感谢K-
--------------------------------------------------
-----------------------

以上来自于谷歌翻译


以下为原文

@ivan.carunas I would appricate if you could start a new thread from next time. Starting a new thread would get immediate attention and most likely to get answer.
 
Anyways regarding your problem there has been changes in the silicon fabrication process which needs update of the files before you generate .mcs and use it for newer XC3S50AN-4TQG144I. .
 
Refer this notice and follow AR
http://www.xilinx.com/support/documentation/customer_notices/xcn14003.pdf
http://www.xilinx.com/support/answers/59572.html
 
I hope once you apply patch this should solve your problem.
 
 
 
-Pratham

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2019-7-29 12:36:20 评论

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