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你好,
我正在为我的一个模块创建一个简单的测试平台。 我正在尝试设计一个执行以下测试工作台: 1)我想最初“重置为高”,{CLK高或低在这种情况下无关紧要。} ,2)“当CLK为高电平时,RESET为低电平,应保持低电平。 附加的是生成的测试信号。 但即使我尝试了几种方法,第二个条件也不满足。 测试台代码alos提供如下。 评论 - 突出显示是我厌倦的另一种方法。 可能我的问题很简单,但我真的需要别人的帮助。 谢谢 模块Top_level_testfixture; //输入reg CCLK; reg RESET; //实例化被测单元(UUT)Top_level_test uut(.CCLK(CCLK),. RESET(RESET)); 初始开始CCLK = 0; RESET = 1; #1 RESET = 0; 永远#1 CCLK = ~CCLK; 结束/ *初始开始@(posedge CCLK); RESET = 0; 结束* / endmodule 以上来自于谷歌翻译 以下为原文 Hello, I am creating a simple test bench for one ofmy module. I am trying to design a test bench which performs following: 1) I want "RESET to be HIGH" initially, { CLK high or low doesnt matter in this case.} ,2) "RESET to be LOW when CLK is HIGH , and should keep it as low. Attached is the generated test signal. But the second condition is not statisfied even if I tried several method. Test bench code alos providing below. Commented- highlighted is another method i tired. May be my question is very simple but I really need some body's help. Thank you module Top_level_testfixture; // Inputs reg CCLK; reg RESET; // Instantiate the Unit Under Test (UUT) Top_level_test uut ( .CCLK(CCLK), .RESET(RESET) ); initial begin CCLK =0; RESET=1; #1 RESET=0; forever #1 CCLK=~CCLK; end /*initial begin @(posedge CCLK); RESET=0; end*/ endmodule |
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9个回答
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嗨,你需要使用always block。
以下是可能对您有帮助的示例代码.http://www.asic-world.com/tidbits/all_reset.html 谢谢,维杰----------------------------------------------- ---------------------------------------------请将帖子标记为 一个答案“接受为解决方案”,以防它有助于解决您的查询。如果一个帖子引导到解决方案,请给予赞誉。 以上来自于谷歌翻译 以下为原文 Hi, You need to use always block. Here is the example code which may help you. http://www.asic-world.com/tidbits/all_reset.htmlThanks,Vijay -------------------------------------------------------------------------------------------- Please mark the post as an answer "Accept as solution" in case it helped resolve your query. Give kudos in case a post in case it guided to the solution. |
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谢谢Vijay。
我仍然没有得到我想要的东西(请参阅附件)。 你能不能一直看看我的更新程序。 `timescale 1ns / 1ps 模块Top_level_testfixture; //输入reg CCLK; reg RESET; //实例化被测单元(UUT)Top_level_test uut(.CCLK(CCLK),. RESET(RESET)); 初始开始CCLK = 0; RESET = 1;结束总是@(posedge CCLK)RESET = 0; 总是开始#1 CCLK = ~CCLK; 结束模块 以上来自于谷歌翻译 以下为原文 Thanks Vijay. I am still not getting what i want( pls see the attachment). Can you please have a look on my updated program with always. `timescale 1ns / 1ps module Top_level_testfixture; // Inputs reg CCLK; reg RESET; // Instantiate the Unit Under Test (UUT) Top_level_test uut ( .CCLK(CCLK), .RESET(RESET) ); initial begin CCLK =0; RESET=1; end always@(posedge CCLK) RESET=0; always begin #1 CCLK=~CCLK; end endmodule |
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请尝试以下方法。
初始RESET = 1; @(posedge CCLK)RESET = 0end initial begin CCLK = 0; 永远#1 CCLK = ~CCLK; 结束 弗拉迪斯拉夫·穆拉文 以上来自于谷歌翻译 以下为原文 Try the following. initial RESET=1; @(posedge CCLK) RESET = 0 end initial begin CCLK =0; forever #1 CCLK=~CCLK; end Vladislav Muravin |
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HiVladislav Muravin,
当我尝试使用你的代码时,我得到了一个稳定的cCLk和RESET。 请查看结果的附件。 我希望我的RESET最初为高。 然后从时钟信号的上升沿开始“RESET设置为低电平”。 谢谢 凯西 以上来自于谷歌翻译 以下为原文 Hi Vladislav Muravin, when i tried using your code, I got a steady cCLk and RESET . please see the attachment for the result. I want my RESET for be High initially. And then "RESET set to LOW" from the positive edge of clock signal onwards. thanks kathy |
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好吧,我输入的速度有点快,但让我们一步一步来。
第一步,创建一个运行时钟。 一种方法是使用以下构造,这至少对我有用: localparamCLK_FREQ = 100.0; // Mhz 初始clk = 0; 最初开始 永远开始 #(500.0 / CLK_FREQ); clk = ~clk; 结束 结束 所以,你现在应该有一个运行时钟。 接下来,你希望你的复位高电平然后在时钟的第一个正边沿变低,最简单的方法是 最初开始 reset = 1; @(posedge clk); reset = 0; 结束 初始构造执行一次,因此,在时钟的第一个上升沿,将复位从1更改为0。 希望这可以帮助 弗拉德 弗拉迪斯拉夫·穆拉文 以上来自于谷歌翻译 以下为原文 Well, I was typing a bit fast, but let's take it step by step. First step, create a running clock. One way to do this is using the following construct, which at least works for me: localparam CLK_FREQ = 100.0; // Mhz initial clk = 0; initial begin forever begin #(500.0 / CLK_FREQ); clk = ~clk; end end So, you should have a running clock by now. Next, you want your reset to bge high and then go low on the very first positive edge of the clock, and the simplest way to do this is initial begin reset = 1; @(posedge clk); reset = 0; end initial construct is executed once and therefore it will, on the first rising edge of the clock, change the reset from 1 to 0. Hope this helps Vlad Vladislav Muravin |
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HiVladislav Muravin,
非常感谢您的帮助。 你有这个代码的结果吗? 附件是我得到的结果。 我的时钟没有发生水平变化。 当我包括下面提供的代码部分时,我的时钟信号是一个稳定的信号,如图所示 附件#1 {但当我删除@(posedge clk); ,时钟级别发生变化,见附件#2} 最初开始 reset = 1; @(posedge clk); reset = 0; 结束 如果我删除上面提供的代码部分,并且仅使用第一个初始代码(时钟通知)运行,那么结果时钟信号具有电平通道。 可能是什么原因?从逻辑上看,一切都很好。 谢谢 凯西 以上来自于谷歌翻译 以下为原文 Hi Vladislav Muravin, Thank you very much for your help. Are you getting result with this code? Attached is the result I am getting. Level changing is not happening for my clock . When I include below provided portion of code ,then my clock signal is a steady signal as shown in attachment #1 { But when I remove @(posedge clk); , clock level change is happening, see attachment #2} initial begin reset = 1; @(posedge clk); reset = 0; end If I remove above provided code portion, and run only with first initial code( clock gneration) , then resulted clock signal have level chanage. What may be the reason? Logically everything looks fine. Thanks kathy |
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凯蒂,
也许最初的@posedgeis没有像我原先打算的那样工作。 在我们的系统中,我们通过虚拟信号模拟复位解除断言,从而启动时钟生成,因此我想简化它。 说实话,这段代码中的一些不是我写的,我从来没有时间完全搞清楚,如果它有效,我已经99%高兴了。 所以这里有一个更完整的代码,你想要的。 也许延迟执行会产生影响。 最初开始 clocks_started = 0; resets_deasserted = 0; #100 clocks_started = 1; #100 resets_deasserted = 1; clk = 0; 结束 initia开始 @(posedge clocks_started); 永远开始 #(500.0 / CLK_FREQ); clk = ~clk; 结束 结束 BR 弗拉德 弗拉迪斯拉夫·穆拉文 以上来自于谷歌翻译 以下为原文 Cathy, Perhaps the initial with @posedge is not working as I'd originally intended. In our system, we model reset deassertion by a dummy signal, which kicks off the clock generation, so I thought to simplify it. To be honest completely, some of this code was not written by me, and I never had time to figure it out completely, and if it works, I am already 99% happy. So here is a more complete code, it you'd like. Perhaps the delayed execution makes a difference. initial begin clocks_started = 0; resets_deasserted = 0; #100 clocks_started = 1; #100 resets_deasserted = 1; clk = 0; end initia begin @(posedge clocks_started); forever begin #(500.0/CLK_FREQ); clk = ~clk; end end BR Vlad Vladislav Muravin |
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HiVladislav Muravin,
我仍然没有得到,我在这里附上我的testbench sorucecode,你能看一下吗? 仿真结果attachmnet#1:当RESET设置为零时,RESET在一定延迟后设置为1。 initial begin clocks_started = 0; RESET = 0; #100 clocks_started = 1; #100 RESET = 1; CCLK = 0; 结束 仿真结果attachmnet#2:当RESET最初置位时,延迟后RESER置为无效。 initial begin clocks_started = 0; RESET = 1; #100 clocks_started = 1; #100 RESET = 0; CCLK = 0;端 谢谢 凯西 Top_level_testfixture.v 1 KB 以上来自于谷歌翻译 以下为原文 Hi Vladislav Muravin, Still I am not getting, I am attaching my testbench sorucecode here with, Can you pls have a look on it? Simulation result attachmnet #1: When RESET is set to zero ,and RESET set to 1 after certain delay. initial begin clocks_started = 0; RESET=0; #100 clocks_started = 1; #100 RESET=1; CCLK=0; end Simulation result attachmnet #2: when RESET asserted initially,and after delay RESER deasserted. initial begin clocks_started = 0; RESET=1; #100 clocks_started = 1; #100 RESET=0; CCLK=0; end thanks kathy Top_level_testfixture.v 1 KB |
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谢谢您的帮助。
测试代码工作正常,问题不在于测试代码。 问题与我的源verilog代码有关。 因为我的RESET不起作用。 以上来自于谷歌翻译 以下为原文 Thanks for the help. test code is working fine, issues was not with the test code. Issues was with my source verilog code. Because of that my RESET was not working. |
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