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我目前正在研究简单的UART发送器,将来自FPGA(SP 605)的8位数据发送到超级终端。 我验证了我的代码,我认为一切都很好,但问题是我没有看到任何进入超级终端!! 我的代码在下面,包含带时钟除数的顶级uart设计,用于管理UART状态的小fsm和ucf文件。 我会感激任何帮助我已经被困了几天,虽然这很容易! 时钟即时使用33Mhz,除数(18d),波特率115200 顶部UART tx -------------------------------------------------- -------------------------------- 图书馆IEEE; 使用IEEE.STD_LOGIC_1164.ALL; 使用IEEE.NUMERIC_STD.ALL; 实体uart_top是 港口 ( clkn:在std_logic中; - 正常clk 33 mhz tx:out std_logic ); 结束uart_top; 架构uart_top的行为是 组件uart_fsm是 港口 ( clk:在std_logic中; - 115200 clk(波特) data_in:在std_logic_vector中(7 downto 0); - 要发送的数据 tx:out std_logic ); 最终组件; 信号计数:整数:= 0; - 时钟除数18 signal clk_i:std_logic:='0'; signal tx_i:std_logic; 开始 过程(clkn)是 开始 如果rising_edge(clkn)那么 count clk_i, - 115200 clk(波特) data_in =>“00110101”, - 要发送的数据 tx => tx_i ); TX FSM -------------------------------------------------- -------------------------------- 图书馆IEEE; 使用IEEE.STD_LOGIC_1164.ALL; 使用IEEE.NUMERIC_STD.ALL; 实体uart_fsm是 港口 ( clk:在std_logic中; - 115200 clk(波特) data_in:在std_logic_vector中(7 downto 0); - 要发送的数据 tx:out std_logic ); 结束uart_fsm; 体系结构uart_fsm的行为是 type state_current是(idle,st0,st1,st2,st3,st4,st5,st6,st7,st8,st9); signal nstate:state_current:= idle; - 下一个州 signal cstate:state_current:= idle; - 当前状态 开始 - 他的过程是决定下一个州 next_state_proc:process(cstate)是 开始 case cstate是 当空闲=> NSTATE NSTATE NSTATE NSTATE NSTATE NSTATE NSTATE NSTATE NSTATE NSTATE NSTATE NSTATE TX TX TX TX TX TX TX TX TX TX TX TX NET“clkn”LOC =“N19”; NET“tx”LOC =“H17”; 以上来自于谷歌翻译 以下为原文 Hello all, Im currently working on simple UART transmitter to send 8 bits of data from FPGA (SP 605) to hyperterminal. I verified my code and i think everything is fine but the problem is that i dont see anything coming in the hyperterminal!!. My code is down below, contains top uart design with clock divisor, small fsm for managing UART states, and ucf file. I'll appreciate any help Ive been stuck for few days now although this is easy!! clock im using 33Mhz, divisor (18d), baud rate 115200 top UART tx ----------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;entity uart_top isport (clkn: in std_logic; -- normal clk 33 mhztx: out std_logic);end uart_top;architecture Behavioral of uart_top iscomponent uart_fsm isport (clk: in std_logic; -- 115200 clk (baud)data_in: in std_logic_vector (7 downto 0); -- data to be senttx: out std_logic);end component;signal count: integer := 0; -- clock divisor 18signal clk_i: std_logic := '0';signal tx_i: std_logic;beginprocess (clkn) i***egin if rising_edge(clkn) then count <= count+1; if count = 18 then clk_i <= clk_i xor '1'; count <= 0; end if; end if; end process; fsm_inst:uart_fsm port map (clk => clk_i, -- 115200 clk (baud)data_in => "00110101", --data to be senttx => tx_i);tx <= tx_i;end Behavioral; FSM ----------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.NUMERIC_STD.ALL;entity uart_fsm isport (clk: in std_logic; -- 115200 clk (baud)data_in: in std_logic_vector (7 downto 0); -- data to be senttx: out std_logic);end uart_fsm;architecture Behavioral of uart_fsm istype state_current is (idle, st0, st1, st2, st3, st4, st5, st6, st7, st8, st9);signal nstate: state_current := idle; -- next statesignal cstate: state_current := idle; -- current statebegin-- his process is to decide on next statenext_state_proc: process (cstate) is begin case cstate is when idle => nstate <= st0; when st0 => nstate <= st1; when st1 =>nstate <= st2; when st2 => nstate <= st3; when st3 => nstate <= st4; when st4 => nstate <= st5; when st5 => nstate <= st6; when st6 => nstate <= st7; when st7 => nstate <= st8; when st8 => nstate <= st9; when st9 => nstate <= idle; when others => nstate <= idle; end case; end process next_state_proc; -- this process set the outpt of each state current_state_proc: process (cstate, data_in) is begin case cstate is when idle => tx <= '1'; --idle state tx sends 1 when st0 => tx<= '0'; -- tx sends 0 befor byte when st1 => tx<= data_in(0); when st2 => tx<= data_in(1); when st3 => tx<= data_in(2); when st4 => tx<= data_in(3); when st5 => tx<= data_in(4); when st6 => tx<= data_in(5); when st7 => tx<= data_in(6); when st8 => tx<= data_in(7); when st9 => tx<= '1'; -- tx sends one after each byte when others => tx<= '1'; end case;end process current_state_proc; clock_control: process(clk) is begin if rising_edge(clk) then cstate <= nstate; end if;end process;end Behavioral;NET "clkn" LOC = "N19";NET "tx" LOC = "H17"; |
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嗨艾哈迈德,
确保进行行为模拟。 如果可行则进行Post PAR模拟。 您可能有时间问题。 Post PAR模拟将告诉你这一点 “我验证了我的代码,我觉得一切都很好”,模拟代码? 尝试使用重置进行设计,并使用此重置初始化计数器和状态机。 你可以使用“sys_reset”LOC =“H8”; 作为系统重置。 始终注册状态机的输出。(在您的情况下注册信号“tx”。) 此外,您的波特率生成也不正确。根据您的代码划分33 MHz,分频器为18 wiil,结果为916.666 KHz。 尝试使用FPGA内部的时钟合成器(PLL / MMCM)来生成buad速率。 你可以尝试除数(143d)。它会产生115384波特而不是115200.我建议你按照Step7 谢谢, 阿克沙伊 在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Hi Ahmed,
Akshay View solution in original post |
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嗨anshpmrl,
是的行为和位置和路线模拟工作正常。如何找到我的时钟的正确除数来获得正确的波特率“115200”,这可能是这里的问题。 以上来自于谷歌翻译 以下为原文 hi anshpmrl, yes both behavioral and post-place and route simulations works fine. How can I find the right divisor for my clock to get the correct baud rate "115200", this could be the issue here. |
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感谢Akshay,我将我的除数改为143d但由于某种原因没有工作。
疯狂的部分是,我重新启动计算机并再次加载位文件,这次它完美地工作! 以上来自于谷歌翻译 以下为原文 thanks Akshay, I changed my divisor to 143d but didnt work for some reason. The crazy part is, I restarted the computer and loaded bit file again it worked perfectly this time!! |
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能告诉我如何将vhdl代码合并到单个项目中
以上来自于谷歌翻译 以下为原文 Can you please let me know how can i combine both the vhdl codes into single project |
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