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[问答] CyPress PSoC1产品系列为I2C提供了多种选择
83 I2C cpu
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在PSOC1中启动I2C
CyPress PSoC1产品系列为在设计中实现I2C提供了多种选择。这些选择以用户模块(UMS)的形式出现在PoSoCdIDE IDE中。I2C通信本身由专用的I2C硬件(HW)块处理,该块从CPU中去除大部分I2C处理负担,释放CPU来做更重要的实时任务。
图1:I2C硬件块
HW块是设计成将PSoC 1与I2C总线接口的串行到并行处理器。HW块通过提供对I2C状态的HW检测和I2C信号的生成的支持来承担CPU的负担。
EZI2CS需要考虑的第一个用户模块是EZI2CS UM。EZI2CS UM仅作为从属设备工作;没有EZI2C的主版本。EZI2CS UM是在I2C硬件块之上的固件层。通过允许用户在用户代码中设置数据结构,并将该结构暴露给I2C主机,它需要最少的用户了解I2C总线是如何工作的。所有I2C事务都通过中断发生在后台。一旦用户模块在主代码中启动,您就不必担心任何I2C功能。
I2CHW
该用户模块是在I2C HW BULL之上的固件层,并且可以用作从属、主或多主从。与EZI2CS不同,该用户模块需要更多的设计器交互。必须检查状态位以查看是否发生I2C事务。主固件还需要检查事务上的错误条件。最后,用户代码必须清除设置的状态位。
一个详细的概述I2C块psoc1例上述用户模块的用法,请参考应用notean50987 -开始使用I2C PSoC®1。

以上来自于百度翻译


     以下为原文
  IF">       Getting Started with I2C in PSoC1
      The Cypress PSoC 1 product family offers several choices for implementing I2C in a design. These choices come in the form of user modules (UMs) that are found in the PSoC Designer IDE. The I2C communication itself is handLED by a dedicated I2C hardware (HW) block which removes much of the I2C processing burden from the CPU, freeing the CPU to do more important real-time tasks.
      Figure 1: I2C Hardware Block
      
      The HW block is a serial to parallel processor designed to inteRFace the PSoC 1 to an I2C bus. The HW block takes the burden off the CPU by providing support for HW detection of I2C status and generation of I2C signals.
      EzI2Cs

      The first user module to consider is the EzI2Cs UM. The EzI2Cs UM operates exclusively as a slave; there is no master version of EzI2C. The EzI2Cs UM is a firmware layer on top of the I2C hardware block. It requires minimal user knowledge of how the I2C bus works by allowing you to setup a data structure in user code, and exposing that structure to the I2C master. All I2C transactions happen in the background through interrupts. You need not worry about any of the I2C functionality once the user module is started in the main code.
      I2CHW
      This user module is a firmware layer on top of the I2C HW bloc and can be used as a slave, master, or multi-master slave. Unlike EzI2Cs, this user module requires more designer interaction. Status bits must be checked to see if an I2C transaction occurred. The main firmware also needs to check for error conditions on a transaction. Finally, user code must clear the status bits that are set.
      For a detailed overview of the I2C block in PSoC1 and example usage of the user modules described above, please refer application note AN50987 - Getting Started with I2C in PSoC® 1.
   
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