Camera Link接收器是否可以工作？

bareil76写道：
好的..让我解释一下它现在是如何工作的。
（这是以这种方式工作）
1）摄像机输入FPGA生成的50Mhz时钟。
相机有一个PLL，将其转换为600Mhz并发回数据。
2）我有这样连接的“Camera Link接收器”
I_SAMPLING_CLK来自FPGA内部的PLL，速度为600Mhz
I_DIV_CLOCK来自FPGA内部的PLL，速度为150Mhz（比数据流的序列化少4倍）
哦，好的，你正在连接到CAMERA，而不是裸露的图像传感器，而且CAMERA有一个Camera Link输出。
那部分不清楚。
现在我的问题是关于上面的＃1。
“由FPGA生成”。
我需要知道它是否可以由一个独立的时钟生成。
我问这个问题因为我看到相位检测器被禁用了。
我需要知道这是否允许我使用独立的时钟。
DISABLE_PD（1'B0），//禁用相位检测器
好吧，我对Camera Link接收器核心一无所知。
但是Camera Link接收器接收来自发送器的像素速率时钟，并且通常使用PLL来合成用于移位的比特率DDR时钟。
并且PLL使用相位检测器，所以为什么要禁用它，我不知道，除了这个接收器将比特率（快速）和像素速率（慢）时钟作为输入，因此不需要
相位检测器。
换句话说：相机的50 MHz时钟可以被认为完全独立于Camera Link接收器所需的时间，因此它的来源可以是任何东西。
无论如何，这是什么相机？
----------------------------是的，我这样做是为了谋生。
在原帖中查看解决方案



以下为原文

bareil76 wrote:
Ok.. let me explain how it is working right now.  (it IS working this way)
 
1) The camera is feed a 50Mhz clock generated by the FPGA. The camera has a PLL, convert this to 600Mhz and sends data back.
 
2) I have a "Camera Link Receiver" connected this way
  
 I_SAMPLING_CLK  is from a PLL inside the FPGA at 600Mhz
 I_DIV_CLOCK          is from a PLL inside the FPGA at 150Mhz (4 times less to deserialize the data stream)
 
Oh, OK, you are interfacing to a CAMERA, not the bare image sensor, and that CAMERA has a Camera Link output. That part was not clear.
 
Now my question is about the #1 above. "generated by the FPGA". I need to know if its ok to be generated by an independant clock.
 
I ask the question because I see the phase detector is disabled. I need to know if this would allow me to use independant clocks.
DISABLE_PD(1'B0),// DISABLE PHASE DETECTOR

Well, I know nothing about that Camera Link receiver core. But a Camera Link receiver takes in the pixel-rate clock from the transmitter and generally uses a PLL to synthesize the bit-rate DDR clock that is used to shift in the bits. And PLLs use phase detectors, so why you'd disable it, I don't know, except that this receiver takes as inputs both the bit-rate (fast) and the pixel-rate (slow) clocks, hence no need for a phase detector.
 
IN OTHER WORDS: the 50 MHz clock TO the Camera can be considered to be completely indepent of what is needed by the Camera Link receiver, and as such its source can be anything.
 
What camera is this, anyway?
----------------------------Yes, I do this for a living.View solution in original post

嗨，
理想情况下，源同步系统（时钟从正在传输数据的设备转发）应该更好，在这些情况下，FPGA的时钟输入应来自发送数据的源。
如果您为源和desitnation提供了不同的时钟源（即使通过相同的频率），则可能存在时序问题。
然而，这完全取决于电路板设计师在编写时序约束时如何处理其设计中的电路板时序。
希望我能正确理解你的问题。
谢谢，AnirudhPS：请将此标记作为答案，以防它有助于解决您的问题。如果帖子引导您找到解决方案，请给予赞誉。



以下为原文

Hi,
 
Ideally, source synchronous system  (clock is forwarded from the device which is transmitting the data)should be better in these cases where the clock input to the FPGA, should originate from the source where the data is being sent from.
 
 
In case you have a different clock source(even through same freq) for the source and the desitnation, then there can be timing problems. However it all depends on how the board designer, has taken care of the board timing in his design while writing the timing constraint.
 
Hope i have understood your question correctly.
Thanks,
Anirudh

PS: Please MARK this as an answer in case it helped resolve your query.Give kudos in case the post guided you to a solution.

你对Camera Link的工作原理有什么看法吗？
----------------------------是的，我这样做是为了谋生。



以下为原文

Do you have any idea at all how Camera Link works?
----------------------------Yes, I do this for a living.

理想情况下，源同步系统（时钟从正在传输数据的设备转发）应该更好，在这些情况下，FPGA的时钟输入应来自发送数据的源。
这个cmos是不可能的。
时钟输出不可用。
你对Camera Link的工作原理有什么看法吗？
这是我第一次使用它。
我读了，但是我想问这个问题，希望能更好地理解它是如何工作的。
然而，这完全取决于电路板设计师在编写时序约束时如何处理其设计中的电路板时序。
我应该考虑什么？
现在，FPGA向CMOS发送50MHz时钟，CMOS以600MHz发送LVDS数据。
有用。
但是，对于下一个应用程序，我需要让时钟独立;
即CMOS板上的时钟与FPGA时钟上的时钟分开。
如果你想到任何有用的东西......欢迎你。



以下为原文

 
Ideally, source synchronous system  (clock is forwarded from the device which is transmitting the data)should be better in these cases where the clock input to the FPGA, should originate from the source where the data is being sent from. It is impossible with this cmos. The clock output is not available. 
 
Do you have any idea at all how Camera Link works?
It is the first time I use this. I read, but I am asking this question in hope to gain a better understanding of how it works.
 
 
However it all depends on how the board designer, has taken care of the board timing in his design while writing the timing constraint. What should I be considering?
 
Right now, the FPGA sends a 50MHz clock to the CMOS and the CMOS sends the LVDS data at 600MHz. It works. However, for the next application, I need to have the clocks independant; i.e. clock on the CMOS PCB separated from the clock onthe FPGA clock.
 
If you think of anything that could help.. you are welcome.

bareil76写道：
现在，FPGA向CMOS发送50MHz时钟，CMOS以600MHz发送LVDS数据。
有用。
但是，对于下一个应用程序，我需要让时钟独立;
即CMOS板上的时钟与FPGA时钟上的时钟分开。
看起来图像传感器具有高速串行数据输出接口。
伴随串行数据线应该是600 MHz速率的时钟。
如果那个时钟不存在，那么你就被冲了 - 你无法做到这一点。
伴随串行数据的时钟可能是像素速率，而不是比特率，在这种情况下，您需要使用PLL从中生成比特率时钟，以便您可以对数据流进行反序列化。
现在我不知道为什么你需要实现Camera Link接收器。
你能解释一下吗？
在我看来你正在构建摄像头，所以你需要一个Camera Link发射器。
在这种情况下，您应该让生活变得轻松，并使用现成的DS90CR287（或两个或三个，具体取决于您使用的Camera Link配置）。
----------------------------是的，我这样做是为了谋生。



以下为原文

bareil76 wrote:
  
Right now, the FPGA sends a 50MHz clock to the CMOS and the CMOS sends the LVDS data at 600MHz. It works. However, for the next application, I need to have the clocks independant; i.e. clock on the CMOS PCB separated from the clock onthe FPGA clock.

It looks like that image sensor has a high-speed serial data output interface. Accompanying the serial data lines should be a clock at the 600 MHz rate. If that clock doesn't exist, then you're hosed -- you cannot make this work.
 
That clock accompanying the serial data may be at the pixel rate, not the bit rate, in which case you'll need to use a PLL to generate the bit-rate clock from it so you can deserialize the data stream.
 
Now I have no idea why you need to implement a Camera Link receiver. Can you explain this? Seems to me that you're building the camera end, so you need a Camera Link transmitter. In which case you should make your life easy and use the off-the-shelf DS90CR287 (or two, or three, depending on which Camera Link configuration you're using).
----------------------------Yes, I do this for a living.

好的..让我解释一下它现在是如何工作的。
（这是以这种方式工作）
1）摄像机输入FPGA生成的50Mhz时钟。
相机有一个PLL，将其转换为600Mhz并发回数据。
2）我有这样连接的“Camera Link接收器”
CAM_LINK＃（。sys_w（1）,. dev_w（4））I_CAM_LINK（ 
.DELAY_INC（1'B0）， 
.DELAY_CE（1'B0）， 
.DISABLE_PD（1'B0），//禁用相位检测器 
//从系统进入设备 
.DATA_IN_FROM_PINS（I_SENSOR_DATIN）， 
.DATA_IN_TO_DEVICE（I_SENSOR_PAR_DAT）， 
.DEBUG_IN（2'B00）， 
.DEBUG_OUT（）， 
//时钟和重置信号 
.CLK_IN（I_SAMPLING_CLK），//来自PLL / MMCM的快速时钟 
.CLK_DIV_IN（I_DIV_CLOCK），//来自PLL / MMCM的慢时钟 
.LOCKED_IN（I_PLL_LOCKED）， 
.LOCKED_OUT（I_SAMPLING_LOCKED_OUT）， 
.CLK_RESET（1'B0），//用于时钟电路的复位信号 
.IO_RESET（I_SAMPLING_RESET） 
）;
数据来自于此
//差分终止 
IBUFDS＃（。DIFF_TERM（1'b1）,. IBUF_LOW_PWR（1'b0）,. IOSTANDARD（“LVDS_25”））I_SENSOR_DAT_IBUFDS（ 
.O（I_SENSOR_DATIN），// BUFFER OUTPUT 
.I（SENSOR_DATIN_P）， 
.IB（SENSOR_DATIN_N）// DIFF_N BUFFER INPUT（直接连接到顶级端口） 
）;
I_SAMPLING_CLK来自FPGA内部的PLL，速度为600Mhz
I_DIV_CLOCK来自FPGA内部的PLL，速度为150Mhz（比数据流的序列化少4倍）
现在我的问题是关于上面的＃1。
“由FPGA生成”。
我需要知道它是否可以由一个独立的时钟生成。
我问这个问题因为我看到相位检测器被禁用了。
我需要知道这是否允许我使用独立的时钟。
DISABLE_PD（1'B0），//禁用相位检测器



以下为原文

Ok.. let me explain how it is working right now.  (it IS working this way)
 
1) The camera is feed a 50Mhz clock generated by the FPGA. The camera has a PLL, convert this to 600Mhz and sends data back.
 
2) I have a "Camera Link Receiver" connected this way
 
CAM_LINK #(.sys_w(1), .dev_w(4)) I_CAM_LINK(      .DELAY_INC(1'B0),      .DELAY_CE(1'B0),      .DISABLE_PD(1'B0),// DISABLE PHASE DETECTOR      // FROM THE SYSTEM INTO THE DEVICE      .DATA_IN_FROM_PINS(I_SENSOR_DATIN),      .DATA_IN_TO_DEVICE(I_SENSOR_PAR_DAT),      .DEBUG_IN(2'B00),      .DEBUG_OUT(),      // CLOCK AND RESET SIGNALS      .CLK_IN(I_SAMPLING_CLK),// FAST CLOCK FROM PLL/MMCM      .CLK_DIV_IN(I_DIV_CLOCK),// SLOW CLOCK FROM PLL/MMCM      .LOCKED_IN(I_PLL_LOCKED),      .LOCKED_OUT(I_SAMPLING_LOCKED_OUT),      .CLK_RESET(1'B0),// RESET SIGNAL FOR CLOCK CIRCUIT      .IO_RESET(I_SAMPLING_RESET)   );The data is coming from this 
 
// Differential Termination   IBUFDS #(.DIFF_TERM(1'b1), .IBUF_LOW_PWR(1'b0), .IOSTANDARD("LVDS_25")) I_SENSOR_DAT_IBUFDS(      .O(I_SENSOR_DATIN),// BUFFER OUTPUT      .I(SENSOR_DATIN_P),      .IB(SENSOR_DATIN_N)// DIFF_N BUFFER INPUT (CONNECT DIRECTLY TO TOP-LEVEL PORT)   ); 
 
 I_SAMPLING_CLK  is from a PLL inside the FPGA at 600Mhz
 I_DIV_CLOCK          is from a PLL inside the FPGA at 150Mhz (4 times less to deserialize the data stream)
 
Now my question is about the #1 above. "generated by the FPGA". I need to know if its ok to be generated by an independant clock.
 
I ask the question because I see the phase detector is disabled. I need to know if this would allow me to use independant clocks.
DISABLE_PD(1'B0),// DISABLE PHASE DETECTOR 
 
 

任何人都可以帮助我吗？



以下为原文

Anyone can help me with that?

bareil76写道：
好的..让我解释一下它现在是如何工作的。
（这是以这种方式工作）
1）摄像机输入FPGA生成的50Mhz时钟。
相机有一个PLL，将其转换为600Mhz并发回数据。
2）我有这样连接的“Camera Link接收器”
I_SAMPLING_CLK来自FPGA内部的PLL，速度为600Mhz
I_DIV_CLOCK来自FPGA内部的PLL，速度为150Mhz（比数据流的序列化少4倍）
哦，好的，你正在连接到CAMERA，而不是裸露的图像传感器，而且CAMERA有一个Camera Link输出。
那部分不清楚。
现在我的问题是关于上面的＃1。
“由FPGA生成”。
我需要知道它是否可以由一个独立的时钟生成。
我问这个问题因为我看到相位检测器被禁用了。
我需要知道这是否允许我使用独立的时钟。
DISABLE_PD（1'B0），//禁用相位检测器
好吧，我对Camera Link接收器核心一无所知。
但是Camera Link接收器接收来自发送器的像素速率时钟，并且通常使用PLL来合成用于移位的比特率DDR时钟。
并且PLL使用相位检测器，所以为什么要禁用它，我不知道，除了这个接收器将比特率（快速）和像素速率（慢）时钟作为输入，因此不需要
相位检测器。
换句话说：相机的50 MHz时钟可以被认为完全独立于Camera Link接收器所需的时间，因此它的来源可以是任何东西。
无论如何，这是什么相机？
----------------------------是的，我这样做是为了谋生。



以下为原文

bareil76 wrote:
Ok.. let me explain how it is working right now.  (it IS working this way)
 
1) The camera is feed a 50Mhz clock generated by the FPGA. The camera has a PLL, convert this to 600Mhz and sends data back.
 
2) I have a "Camera Link Receiver" connected this way
  
 I_SAMPLING_CLK  is from a PLL inside the FPGA at 600Mhz
 I_DIV_CLOCK          is from a PLL inside the FPGA at 150Mhz (4 times less to deserialize the data stream)
 
Oh, OK, you are interfacing to a CAMERA, not the bare image sensor, and that CAMERA has a Camera Link output. That part was not clear.
 
Now my question is about the #1 above. "generated by the FPGA". I need to know if its ok to be generated by an independant clock.
 
I ask the question because I see the phase detector is disabled. I need to know if this would allow me to use independant clocks.
DISABLE_PD(1'B0),// DISABLE PHASE DETECTOR

Well, I know nothing about that Camera Link receiver core. But a Camera Link receiver takes in the pixel-rate clock from the transmitter and generally uses a PLL to synthesize the bit-rate DDR clock that is used to shift in the bits. And PLLs use phase detectors, so why you'd disable it, I don't know, except that this receiver takes as inputs both the bit-rate (fast) and the pixel-rate (slow) clocks, hence no need for a phase detector.
 
IN OTHER WORDS: the 50 MHz clock TO the Camera can be considered to be completely indepent of what is needed by the Camera Link receiver, and as such its source can be anything.
 
What camera is this, anyway?
----------------------------Yes, I do this for a living.

哦，好的，你正在连接到CAMERA，而不是裸露的图像传感器，而且CAMERA有一个Camera Link输出。
那部分不清楚。
对..抱歉。
无论如何，这是什么相机？
看这里
谢谢你的方式......这就是我需要的答案。
我将尝试在此相机接收器链接上提供更多信息。
我想完全理解它是如何工作的。



以下为原文

Oh, OK, you are interfacing to a CAMERA, not the bare image sensor, and that CAMERA has a Camera Link output. That part was not clear.
 
Yes.. sorry about that.  
 
 
What camera is this, anyway?
 
Look here
 
Thanks by the way... this is the answer I needed.
 
I will try to fectch more info on this camera receiver link. I'd like to understand fully how it works.