如何确定峰值信号的上升/下降时间？

yigitt写道：
大家好，
我开发了一个用于Spartan 3e套件的VHDL PWM生成算法，一切都是预期的。
但我想了解这个信号的上升/下降时间，模拟显示理想的行为，但在范围上我看到的东西不同。
从理论上讲，如何确定峰值信号的上升/下降时间？
我把C9作为时钟源并进行倍频。
我希望有经验的用户提供一些指导。
干杯。
您需要快速的“范围探测以及快速”范围。
您需要一个非常短的路径，从接地点非常靠近要测量的信号和探头的地面。
所有Tek和安捷伦的示波器探头都配有一个套件，其中包括一个小弯头弹簧，它可以绕探头尖端滑动，并有一个接地的点。
在约翰逊和格雷厄姆的“高速数字设计”一书中，对这个话题进行了很好的讨论。
买这本书。
阅读。
----------------------------是的，我这样做是为了谋生。



以下为原文

yigitt wrote:
Hi all,
 
I developed a PWM generation algorithm in VHDL for Spartan 3e kit and everything is expected. But I would like to learn about the rise/fall times of this signal, simulation shows the ideal behavior but on the scope I see things different. From the theoretical approach how can I determine the rise/fall times of a peak signal ?
 
I take C9 as the clock source and do frequency multiplication.
 
I would appreciate some guidance from experienced users.
 
Cheers.

You need a fast 'scope probe along with a fast 'scope.
 
You need a VERY short path from a ground point that is very near the signal to measure and the probe's ground. All Tek and Agilent 'scope probes come with a kit which includes a little curlicue spring guy which slips around the probe tip and has a point that goes to the ground.
 
There is a great discussion of this very topic in Johnson and Graham's "High Speed Digital Design" book.  Buy the book. Read it.
----------------------------Yes, I do this for a living.

从产品的数据表中我找不到有关信号的最小/理想上升/下降时间的任何信息。
由于它来自切换到开/关的时间，因此应该有最小值？



以下为原文

From the datasheet of the product I couldnt find any info regarding the minimum/ideal rise/fall times of a signal. Since it originates from the time for the switch to on/off, there should be a minimum value for this ?

Y，
信号完整性取决于负载，pcb，配置等。
它由Xilinx提供的IBIS模型指定。
使用它们。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

y,
 
Signal Integrity depends on load, pcb, configuration, etc.
 
It is specified by the IBIS models Xilinx delivers.
 
Use them.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

你能解释为什么你对PWM输出的上升和下降时间感兴趣吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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你读过手册了吗？
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以下为原文

Can you explain why you are interested in the rise and fall times of your PWM output?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我打算生成一个子ns脉冲。



以下为原文

I am planning to generate a sub-ns pulse.

最小上升/下降时间没有指定或引用，因为它们是高度可变的，并且这个特性没有在生产中测试。个人而言，我会使用FPGA产生一个控制位置（但不是宽度）的脉冲，并使用off-
芯片逻辑和布线产生细长脉冲。
例如：
FPGA 2-in XOR门
------ + + ------------- + 
|
B1 |
| 
|
A + --------> + + ------------>脉冲窄
+ ------ + |
|
+  -  + 
|
+ --------> + |
---- + + ----- 
|
B2 |
|
------ + + ------------- +
如果跟踪段B2比跟踪段B1长3英寸，那么每次FPGA输出切换逻辑电平时，您都可以获得550pS脉冲输出。
这假设XOR门足够快以产生如此窄的脉冲，并且在传统的FR-4电路板上使用每英尺2.2nS的标称电子速度和70欧姆的铜互连。
通过改变B2和B1的差分走线长度，可以非常精确地控制不同的脉冲宽度。
您不需要使用电路板，您可以在原型板上使用电线，但仍能产生良好的效果。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
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我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Minimum rise/fall times are not specified or quoted because they are highly variable and this characteristic is not tested in production.

Personally, I would use an FPGA to generate a pulse with control over the position (but not width), and use off-chip logic and wiring to generate a slender pulse.  For example:
 
FPGA                    2-in XOR gate
------+                +-------------+
      |          B1    |             |
      | A    +-------->+             +------------>  narrow pulse
      +------+         |             |                 +-+
      |      +-------->+             |             ----+ +-----
      |          B2    |             |
------+                +-------------+
 
If trace segment B2 is longer than trace segment B1 by 3 inches, then you can expect a 550pS pulse output every time the FPGA output switches logic level.  This assumes that the XOR gate is fast enough to generate such a narrow pulse, and uses the nominal electron speed of 2.2nS per foot with 70-ohm copper interconnect on conventional FR-4 circuit boards.
 
By varying the differential trace length of B2 and B1, different pulse widths can be controlled with very good precision.  You don't need to use circuit boards, you can use wires on a prototyping board and still produce good results.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

感谢Bob的回复。
不幸的是我需要调整脉冲宽度，因此B1和B2技巧可能无法正常工作。
但是因为阻抗在这里很重要，也许你的方法可以用某种数字电位器实现？



以下为原文

Thank you for  the informative reply Bob. Unfortunately I need to adjust the pulse width as well thus B1 and B2 trick might not work. But since it is the impedance what counts here, maybe your approach can be implemented with some sort of a digital pot ?
 

你需要多少精确控制脉冲宽度？
这是异步设计，对FPGA设计几乎没有任何影响，只是为了清楚。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

How fine a control of the pulse width do you need?  This is asynchronous design, and has little if any bearing on FPGA design, just to be clear.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

我需要一个0到10 ns的可调宽度。



以下为原文

I need  an adjustable width of 0 - 10 ns.
 

0-10 nS是调整范围。
您需要什么样的粒度或分辨率？
您的要求越苛刻，您需要做的工作就越多。
我描述的电路可用于从宽脉冲产生窄脉冲。
请记住，用于生成和传播窄（sub-nS）脉冲的电路将是深奥的低压电路。
您的要求适用于上升和下降时间远短于最小脉冲宽度的设备。
2.5V CMOS或LVTTL逻辑器件无法根据需要产生如此窄的脉冲。
您可能需要低压差分信号设备来满足您的要求。
单端信号传输不仅比差分信号更慢（更低带宽）（所有其他条件相同），但单端信令对电压偏移和噪声非常敏感* * * * * * * *会导致脉冲收缩或脉冲
生长。
您还需要一个非常漂亮（且价格昂贵）的“示波器和探头套件”来准确测量您的信号。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

0-10 nS is the range of adjustment.  What granularity, or resolution, do you need?  The more demanding your requirements, the more work you will need to do to fulfill them.
 
The circuit I described is useful for generating narrow pulses from wide pulses.  Keep in mind that circuitry for generating and propagating narrow (sub-nS) pulses will be esoteric, low-voltage circuitry.  Your requirements are for devices with rise and fall times much shorter than your minimum pulse width.  2.5V CMOS or LVTTL logic devices cannot generate such narrow pulses as you require.
 
You will likely need low voltage differential signaling devices to meet your requirements.  Not only is single-ended signaling slower (lower bandwidth) than differential signaling (all else being equal), but single-ended signaling is very sensitive to voltage offsets and noise which *will* (not *may*) result in pulse shrinkage or pulse growth.
 
You will also need a very very nice (and expensive) kit of 'scope and probe(s) to accurately measure your signals.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

您是否知道任何可以快速切换的XOR门？
我环顾四周，但似乎无法发现一个。
分辨率约为1ns。



以下为原文

Are you aware of any XOR gates that can do the swithcing that fast ? I looked around but doesn't seem to be able to spot one.
 
Resolution will be around like 1ns.

y33t写道：
您是否知道任何可以快速进行切换的XOR门？
我环顾四周，但似乎无法发现一个。
分辨率约为1ns。
你现在看到你的运动徒劳无功吗？
----------------------------是的，我这样做是为了谋生。



以下为原文

y33t wrote:
Are you aware of any XOR gates that can do the swithcing that fast ? I looked around but doesn't seem to be able to spot one.
 
Resolution will be around like 1ns.

Do you now see the futility of your exercise?
----------------------------Yes, I do this for a living.

一个非常*经验丰富的模拟设计师*可能会尝试采用CML输出的串行选通电流树配置中的分立晶体管进行定制设计。
这不适合没有经验的设计师。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

A *very* experienced analogue designer *might* try a custom design from discrete transistors in a series-gated current tree configuration, with CML outputs.  This is not for the inexperienced designer.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

bassman59写道：
y33t写道：
您是否知道任何可以快速进行切换的XOR门？
我环顾四周，但似乎无法发现一个。
分辨率约为1ns。
你现在看到你的运动徒劳无功吗？
不，我没有，这是因为你错了。经验丰富的人已经指示我进入一些门，只有几个pS切换时间;
而不是像你一样造成信息污染。
如果你知道如何搜索或备用几秒而不是直接评论，假设你知道答案，那就不是这样了。保持“为自己的生活做这件事”只是尽量不要误导人们对你的看法
不知道。
这是可行的。



以下为原文

bassman59 wrote:

y33t wrote:
Are you aware of any XOR gates that can do the swithcing that fast ? I looked around but doesn't seem to be able to spot one.
 
Resolution will be around like 1ns.

Do you now see the futility of your exercise?

No I don't and it's because you are wrong.

Experienced people directed me to some gates with only a few pS switching times already ; instead of causing information pollution like you. If you knew how to search or spare a couple of seconds instead of directly commenting by assuming you know the answer, this wouldn't be the case.

Keep on 'doing that for your own living' just try not to misdirect people on things you have no idea about. It's doable.

eteam00写道：
一个非常*经验丰富的模拟设计师*可能会尝试采用CML输出的串行选通电流树配置中的分立晶体管进行定制设计。
这不适合没有经验的设计师。
- 鲍勃埃尔金德
你可能是对的，我不是模拟设计师。
我会更多地研究你的建议，也许我可以想出一个解决方案。
感谢您提供丰富的回复。



以下为原文

eteam00 wrote:
A *very* experienced analogue designer *might* try a custom design from discrete transistors in a series-gated current tree configuration, with CML outputs.  This is not for the inexperienced designer.
 
-- Bob Elkind

You may be right, I am not an analog designer. I will research your suggestion more and maybe I can come up with a solution. Thank you for your informative replies.
 

y33t写道：
继续“为自己的生活做这件事”，尽量不要误导人们你不知道的事情。
这是可行的。
这个怎么样：
只需这样做，然后在完成后发布结果。
举个例子，我真的很想看到你提出的问题。
我们会等。
----------------------------是的，我这样做是为了谋生。



以下为原文

y33t wrote:
Keep on 'doing that for your own living' just try not to misdirect people on things you have no idea about. It's doable.

How about this:
 
Just do it, and then post your results when you are complete. I, for one, am actually interested in seeing what you come up with.
 
We'll be waiting. 
----------------------------Yes, I do this for a living.

不，我没有，这是因为你错了。
我不太确定。
经验丰富的人已经指示我进入一些只有几个pS切换时间的门;
“几ps”？
真？
我非常怀疑。
即使芯片直接连接到电路板以避免封装寄生，板级互连也不支持“简单”二进制数字逻辑，具有您建议的切换时间。
而不是像你一样造成信息污染。
如果你知道如何搜索或备用几秒而不是直接评论，假设你知道答案，那就不是这样了。保持“为自己的生活做这件事”只是尽量不要误导人们对你的看法
不知道。
这是可行的。
深吸一口气。
巴斯曼正在努力帮助您避免花费大量时间和金钱来追求不切实际的目标。
也许你应该认为，在你判断贝斯曼是某种傻瓜之前，他的经历至少与你的经历一样深远和广泛。
他的风格不是很流畅，但他的评论几乎总是知识渊博，乐于助人。
在任何情况下，如果可能且实用的话，设计一个电路可以切换“几ps”的电路板要比你的技能和专业知识所支持的要求更高。
我知道这是因为在这个级别的设计工程中受过教育的人不会问你所问的问题（到目前为止）。
通过学习科学和将这种学习付诸实践，您可以获得所需的专业知识。
单独学习并不足以取得圆满成功。建议您雇用经验丰富的帮助来规划和实施项目目标。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
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以下为原文

No I don't and it's because you are wrong.
 
I would not be so certain.

Experienced people directed me to some gates with only a few pS switching times already ;
 
"a few ps" ?  Really?  I am very skeptical.  Even with a die attached directly to a board to avoid package parasitics, board level interconnect will not support "simple" binary digital logic with such switching times as you suggest.
 
instead of causing information pollution like you. If you knew how to search or spare a couple of seconds instead of directly commenting by assuming you know the answer, this wouldn't be the case.

Keep on 'doing that for your own living' just try not to misdirect people on things you have no idea about. It's doable.
 
Take a deep breath.  Bassman is trying to help you avoid spending significant time and money pursuing unrealistic goals.  Perhaps you should consider that his experience is at least as deep and broad as yours, before you judge bassman to be some sort of fool.  His style is not very smooth, but his comments are almost always knowledgeable and helpful.
 
In any case, designing a board with circuits which switch in "a few ps" -- if possible and practical -- is far more demanding than your skills and expertise can support.  I know this because someone schooled in this level of design engineering would not be asking the questions you have asked (so far).  The expertise you need is gained  both by studying  the science and by committing this learning to practice.  Studying alone is not enough to achieve a successful conclusion.

Suggest you hire the experienced help you need to plan and implement your project goals.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

巴斯曼的经历可能比他的领域深得多，毫无疑问。
令我感到沮丧的是，一个有智慧的人应该鼓励人们而不是试图夸大工作并试图证明他是在山顶。
毕竟他所做的就是将各个部分组合在一起或修改由其他人完成的事情。只需要搜索HMC851LC3C并检查数字，我很确定任何具有基本电子技能的人都可以生成让我们说100pS宽度的脉冲
有你的建议的设备。
很明显，他所谓的“徒劳”被很久以前的其他人所思考和实施。
一个有智慧的人不应该假设他已经更新了信息并直接分享，如果他没有 - 那么。
这是我遇到和工作过的经验丰富的人的默认行为和倾向。对我来说;
我没有任何我不使用的信息，信息是免费的和可访问的我只在我需要的时候学习东西（或者就这个主题问更多有经验的人）。我尊重你们在这里所做的工作，但我鼓励你们
在没有充分理由的情况下鼓励人们，而不是以某种方式使他们失去动力。谢谢大家。和平。



以下为原文

Bassman's experience is probably much deeper than mine in his field there is no question about that. What I am frustrated about is that a guy at that wisdom should be encouraging people rather than trying to exaggerate the work and trying to show that he is at the top of the mountain. After all what he does is bringing pieces together or modifying things which were done by some other people.

Just do a search for HMC851LC3C and check the numbers, I am pretty sure that anybody with basic electronics skills can generate let's say 100pS width pulse with that device with your suggestion. Obviously, what he labelled as 'futile' is thought and implemented by some other people long time ago. A guy at that wisdom shouldn't assume he has updated information and share it directly if he -simply- hasn't. That was the default behavior and tendency of the -really- experienced folks I met and worked with.

And for me ; I don't hold any information that I don't use, information is free and accessible I learn things (or ask more experienced people on that topic) only when I need to.

I respect the work you all do here but I encourage you to encourage people while you can rather than somehow demotivating them without solid reasons.

Thank you all.
Peace out.
y.