发 帖  
原厂入驻New
[问答] 请问是否有NoBL SRAMs的参考方案设计推荐文件?
614 pcb设计 FPGA
分享
你好,
我将使用一个NoBL SRAM(CY7C147BV33)在我的PCB设计中使用VixTy-5 FPGA。是否有NoBL SRAMs的参考方案设计推荐文件?
最好的,

以上来自于百度翻译


     以下为原文
  Hello,
    I will use a NoBL SRAM (CY7C1474BV33) in my PCB design with Virtex-5 FPGA. Is there any reference schematic design recommendation document for NoBL SRAMs?
    Best,
0
2019-7-4 09:47:52   评论 分享淘帖 邀请回答

相关问题

1个回答
嗨,Selmanerg,
我们很抱歉地说,目前我们没有任何参考方案设计NoBL SRAM。然而,由于部分工作在相对较低的频率,我们可以连接它的引脚到引脚(从FPGA到内存)。但我们总是建议客户进行相同的SI模拟,并检查信号是否良好,有或没有终止。
如果您想添加端接电阻,则通常建议在时钟和数据信号上使用串联终止或上拉(下拉)终止,并根据信号完整性如何来选择地址和控制信号。请检查此链路F。或更多细节:
HTTP://www. CyPress?COM/?ID=4和;RID=30075
一件事,你可能要小心的是解耦电容器将在设计中使用。我想下面的文章将帮助您设计去耦电容器。
我们也可以审查你的示意图,一旦你做了同样的事情。
当做
岩溶岩

以上来自于百度翻译


     以下为原文
    Hi Selmanerg,
     We are sorry to say that currently we don't have any reference schematic design for NoBL SRAM. However, since the part operates at comparatively low frequency, we can connect it pin to pin (from FPGA to Memory). But we always recommend our customers to perform SI Simulations for the same and check if the signals look good with or without terminations.       

     If you would like to add termination resistors, then  it is typically recommended to use series termination or pull-up (pull-down) termination on the clocks and the data signals, and optionally on the address and the control signals depending on how the signal integrity looks. Please check this link for more details:       

     http://www.cypress.com/?id=4&rID=30075       

     One thing which you might have to take care would be the decoupling capacitors to be used in the design. I think the following article would help you with the Design of Decoupling Capacitors         
 
     We can also review your schematic once you are done with the same.
     Regards
     PSoCRocks
            
2019-7-4 09:57:48 评论

举报

只有小组成员才能发言,加入小组>>

362个成员聚集在这个小组

加入小组

创建小组步骤

关闭

站长推荐 上一条 /10 下一条

快速回复 返回顶部 返回列表