为什么在设计中混合正负边缘触发器不起作用？

我正在使用斯巴达6。
在本文末尾的代码片段中，我使用的是使用正边沿驱动某些寄存器的时钟，以及使用负边沿的其他寄存器。
正边沿和负边沿驱动触发器在模块“存储器”内一起使用，以在两个边缘上存储输入。
状态机是16位加法器，每个位存储在“存储”元素中。
“storage”元素的4个输出在LED上设置，以便我可以看到结果。
我看到的问题是我将正确地看到counterdataout [12：0]按预期计数，但最重要的位counterdataout [15:13]将陷入相同的状态;
就好像在一定数量的这些“存储”元素之后，附加的“存储”元素停止正常工作。
如果我使用单边触发器（正边沿或负边沿）实现模块“存储”，则状态机的所有16位都按预期计数。
所以我的问题是，为什么在设计中混合正负边缘触发器不起作用？
模块存储（输入线clk，输入线数据，输出线数据输出）;
reg r1，r2;
总是@（posedge clk）r1总是@（negedge clk）r2指定dataout = clk？
r1：r2;
/ *取消注释使用正边缘触发器。
reg r;
总是@（posedge clk）r赋值dataout = r;
* / / *取消注释使用负边缘触发器。
reg r;
总是@（negedge clk）r assign dataout = r;
* / endmodulemodule main（输入线clk，输出线[3：0] leds）;
//状态机，它是一个计数器逻辑//其状态的每个位都存储在每个存储模块中。
电线[15：0]反击;
wire [15：0] counterdataout;
assign counteratat = counterdataout + 16'b1;
//设置4位LED。
assign leds = counterdataout [15:12];
存储计数器0（clk，counterdatain [0]，counterdataout [0]）;
存储计数器1（clk，counterdatain [1]，counterdataout [1]）;
存储计数器2（clk，counterdatain [2]，counterdataout [2]）;
存储计数器3（clk，counterdatain [3]，counterdataout [3]）;
storage counter4（clk，counterdatain [4]，counterdataout [4]）;
存储计数器5（clk，counterdatain [5]，counterdataout [5]）;
存储计数器6（clk，counterdatain [6]，counterdataout [6]）;
存储计数器7（clk，counterdatain [7]，counterdataout [7]）;
存储计数器8（clk，counterdatain [8]，counterdataout [8]）;
存储计数器9（clk，counterdatain [9]，counterdataout [9]）;
存储计数器10（clk，counterdatain [10]，counterdataout [10]）;
存储计数器11（clk，counterdatain [11]，counterdataout [11]）;
存储计数器12（clk，counterdatain [12]，counterdataout [12]）;
存储计数器13（clk，counterdatain [13]，counterdataout [13]）;
存储计数器14（clk，counterdatain [14]，counterdataout [14]）;
存储计数器15（clk，counterdatain [15]，counterdataout [15]）;
endmodule



以下为原文

I am using a Spartan 6.

In the code snippet at the end of this post, I am using a clock that drives some registers using a positive edge, and other registers using a negative edge.

A positive edge and a negative edge driven flipflop, are used together within the module "storage" to store an input on both edges.

The state machine is a 16 bits adder, for which each bit is stored in a "storage" element.

The output of 4 of the "storage" element is set on the LEDs so that I can visualize the result.

The issue that I am seeing is that I will correctly see counterdataout[12:0] count up as expected, but the most significant bits counterdataout[15:13] will just get stuck with the same state; it is as if after a certain number of these "storage" elements, additonal "storage" elements stop working correctly.

If I implement the module "storage" using a single flipflop that is either positive edge or negative edge, all the 16 bits of the state machine count up as expected.


So my question is, why mixing positive and negative edge flipflop in a design does not work ?







module storage(
    input wire clk,
    input wire datain,
    output wire dataout
    );
   
    reg r1, r2;
   
    always @(posedge clk) r1 <= datain;
   
    always @(negedge clk) r2 <= datain;
   
    assign dataout = clk ? r1 : r2;
   
   
    /* Uncomment to use positive edge flipflop.
   
    reg r;
   
    always @(posedge clk) r <= datain;
   
    assign dataout = r; */
   
   
    /* Uncomment to use negative edge flipflop.
   
    reg r;
   
    always @(negedge clk) r <= datain;
   
    assign dataout = r; */
   
endmodule


module main(
    input wire clk,
    output wire[3:0] leds
    );
   
    // State machine which is a counter logic
    // for which each bit of its state is stored
    // in each of the storage modules.
    wire[15:0] counterdatain;
    wire[15:0] counterdataout;
    assign counterdatain = counterdataout + 16'b1;
   
    // Set the 4 bits leds.
    assign leds = counterdataout[15:12];
   
    storage counter0(clk, counterdatain[0], counterdataout[0]);
    storage counter1(clk, counterdatain[1], counterdataout[1]);
    storage counter2(clk, counterdatain[2], counterdataout[2]);
    storage counter3(clk, counterdatain[3], counterdataout[3]);
   
    storage counter4(clk, counterdatain[4], counterdataout[4]);
    storage counter5(clk, counterdatain[5], counterdataout[5]);
    storage counter6(clk, counterdatain[6], counterdataout[6]);
    storage counter7(clk, counterdatain[7], counterdataout[7]);
   
    storage counter8(clk, counterdatain[8], counterdataout[8]);
    storage counter9(clk, counterdatain[9], counterdataout[9]);
    storage counter10(clk, counterdatain[10], counterdataout[10]);
    storage counter11(clk, counterdatain[11], counterdataout[11]);
   
    storage counter12(clk, counterdatain[12], counterdataout[12]);
    storage counter13(clk, counterdatain[13], counterdataout[13]);
    storage counter14(clk, counterdatain[14], counterdataout[14]);
    storage counter15(clk, counterdatain[15], counterdataout[15]);
   
endmodule