使用ChipScope观察到的SFP，SMA GTP上的数据流错误

N，
如果没有抖动测量包，用示波器测量抖动可能是个问题。
你会低估相当大的抖动。
将时钟传递给PLL，然后通过结构资源传递到GT上会增加抖动，并且不会是最佳的（正如您所发现的那样）。
你是如何解决的？
好吧，不要这样做：GT的参考时钟有它们特定的时钟输入和资源，因为必须将一个非常好的时钟信号直接输入GT磁贴而不会被所有其他切换损坏
继续！
看一下在FPGA_Editor中采用的特定路线：有没有办法让GT中的迹象更加优化？
此设计中使用了哪些资源，您可以使用哪些其他资源？
区域时钟缓冲器和其他资源可能从所有其他开关（CLB和IOB）上施加较少的抖动。
它不是最佳的，但也许甚至可以使用短的局部互连线？
同样，对于不良的设计实践，所有上述都是创可贴，不建议这样做（为了获得最佳的抖动容限和抖动产生）。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

n,
 
Measuring jitter with an oscilloscope can be a problem, if it doesn't have a jitter measurement package on it.  You will be underestimating the jitter by a fairly large amount.
 
Passing a clock to a PLL, then onto the GT, through the fabric resources is going to add jitter, and is not going to be optimal (as you have discovered).

How do you fix it?  Well, do not do it that way:  the reference clocks for the GT's have their specific clock inputs, and resources just because one must get a very good clock signal directly into the GT tile without having it get corrupted by all the other switching that is going on!
 
Look at the specifc routes taken in FPGA_Editor:  is there a way to get the signsls in and to the GT which is more optimal?  What resources are used in this design, and what other resources could you use?  Regional clock buffers, and other resources may have less jitter imposed on them from all the other switching going on (both CLB's and IOB's).  It isn't optimal, but maybe there is even a short local interconnect wire that may be used?

Again, all of the above is a band-aid, for a poor design practice, that is not recommended (for optimal jitter tolerance, and jitter generation).
 
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

奥斯汀感谢你们的地震反应。
关于抖动测量方法：我使用数字示波器示波器观察迹线并在包络模式下使用光标。
此模式记住信号的最大和最小偏移。
所以有人可以测量选择以选择抖动。
12,5ns（参考时钟80MHz）的80ps抖动是否正常？
关于其余部分：我正在考虑使用80MHz的外部源（如果我能找到一个），以便通过SMA连接器直接驱动MGT TILE。
我想这没关系。
但不幸的是，我不明白为什么通过在芯片上使用额外的PLL我没有得到“好”的信号。
如果可以，请告诉我。
再次感谢你。



以下为原文

Austin thank you for the quake response.

About the jitter measuring method:
    I used a Digital Scope Oscilloscope by watching the trace and using cursors in envelope mode.
This mode remembers the maximum and the minimum excursions of the signal.
So someone can measure the pick to pick jitter.
Is the 80ps jitter of the 12,5ns (reference clock 80MHz) ok?

About the rest:
    I am thinking of using an external source of 80MHz (if I can find one) in order to drive the MGT TILEs directly via SMA connectors. I think this will ok.
But unfortunately I dont understand why by using an additional on the chip PLL I am not getting a "good" signal.
Please Enlighten me if you can.

Thank you again.

您的抖动至少是您所描述的方法测量的2倍....
抖动测量是一门艺术。
它需要适当的设备。
MGT的专用时钟输入引脚具有任何资源的最低可能添加抖动。
一旦你使用时钟进入FPGA并使用任何全局时钟资源，你将时钟通过许多缓冲区到达芯片的中心，然后到达PLL，然后返回到芯片的中心
。
所有这些缓冲意味着每一步都有基板噪声和其他信号耦合的抖动。
尽管时钟线在芯片上被屏蔽，并且每种技术都用于防止过多的抖动，但是不可能不添加抖动。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

Your jitter is at least 2X what you are measuring by the method you describe....
 
Jitter measurement is an art.  It requires the proper equipment.

The dedicated clock input pins for the MGT's have the lowest possible added jitter of any resource.

Once you get onto the FPGA with a clock, and use any global clock resource, you pass the clock through many buffers to get to the center of the chip, and then get to the PLL, and then get back to the center of the chip.  All that buffering means that there is jitter added at every step by substrate noise, and coupling from other signals.  Even though the clock lines are shielded on die, and every technique is used to prevent too much added jitter, it si impossible not to be adding jitter.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose

谢谢Austin。我认为没有办法从200MHz创建80MHz参考时钟，以便使用所需的输出（80MHz）来驱动MGT，而不会增加临界量的抖动。所以继续使用的唯一方法就是使用
使用SMA连接器的LVDS输出的外部时钟源，或者只需连接振荡器来驱动MGT。如果有任何其他建议，请回复。



以下为原文

Thank you Austin.

I think there is no way to create the 80MHz reference clock from the 200MHz in order to use the desired output (80MHz) to drive the MGTs without adding a critical amount of jitter.

So the only way to continue is to use an external clock source with an LVDS output using the SMA connectors, or just connect an oscillator to drive the MGTs.

Please reply if there are any other suggestions.

N，
看起来您必须根据用户指南提供最佳时钟，以获得最佳的发送抖动生成和最佳输入抖动容差：是的。
有时候没有捷径可以采用正确的（推荐的）方式。
如果您可以控制链路的两端，并且您可以控制信号完整性，则可以接受更高的抖动时钟（或者您的链路协议中具有纠错功能）。
但是，显然，这不是这种情况。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

n,
 
It looks like you will have to provide a best clock, per the user's guide, to get the optimal transmit jitter generation, and best input jitter toleranace:   yes.
 
Sometimes there are no shortcuts to doing it the right (recommended) way.

In cases where you have control over both ends of the link, and you have control over the signal integrity, a higher jitter clock may be acceptable (or where you have error correction capabilities in your link protocol).
 
But, clearly, this is not the case here.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose