请问如何才能从verilog模块生成中断？

Vishysub，
“读取FPGA外部引脚上的频率”是什么意思？
你的意思是“计算脉冲（或边缘）之间的时钟周期”？
该模块具有16个外部上升沿的ref计数，并在50Mhz的ref时钟内部计数。
在16时钟，它将值锁存到寄存器中。
我不愿意猜测这意味着什么。
请重新说明此说明。
听起来这个模块是作为状态机实现的。
您应该发布模块代码（以及预期设计功能的更新说明）。
也许Gabor和我可以像你之前在这个论坛中的主题一样彻底地解决这个问题！
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Vishysub,
 
What does "read a frequency on an external pin of the FPGA" mean?
Do you mean "count clock cycles between pulses (or edges)" ?
 
The module has a ref counts 16 external rising edges and counts internal at a ref clock of 50Mhz. At the 16 clock it latches the value into a register.
 
I am reluctant to guess at what this means.  Please re-phrase this description.
 
It sounds like the module is implemented as a state machine.  You should post your module code (along with an updated description of your intended design function).  Maybe Gabor and I can pick this problem apart as thoroughly as your previous thread in this forum!
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

eteam00写道：
Vishysub，
“读取FPGA外部引脚上的频率”是什么意思？
你的意思是“计算脉冲（或边缘）之间的时钟周期”？
该模块具有16个外部上升沿的ref计数，并在50Mhz的ref时钟内部计数。
在16时钟，它将值锁存到寄存器中。
我不愿意猜测这意味着什么。
请重新说明此说明。
听起来这个模块是作为状态机实现的。
您应该发布模块代码（以及预期设计功能的更新说明）。
也许Gabor和我可以像你之前在这个论坛中的主题一样彻底地解决这个问题！
- 鲍勃埃尔金德
对不起鲍勃，我会试着解释一下，
1.我已生成一个参考时钟，即50Mhz。有一个24位自由运行计数器，用于计算该时钟的上升沿。
2.外部时钟是要测量的时钟，在接收外部时钟的16个上升沿后，我锁存24位计数器。
模块捕获（
输入ref_clk，// 50 MHz ref
输入in_clk，// freq为
输入重置，
输出reg [23：0] f_meas 
）;
reg [23：0]计数;
reg [3：0] presc;
最初开始
f_meas = 0;
presc = 0;
//清除预分频器
结束
//在ref时钟上升沿
总是@（posedge ref_clk）开始
if（reset）开始//同步复位
计数



以下为原文

eteam00 wrote:
Vishysub,
 
What does "read a frequency on an external pin of the FPGA" mean?
Do you mean "count clock cycles between pulses (or edges)" ?
 
The module has a ref counts 16 external rising edges and counts internal at a ref clock of 50Mhz. At the 16 clock it latches the value into a register.
 
I am reluctant to guess at what this means.  Please re-phrase this description.
 
It sounds like the module is implemented as a state machine.  You should post your module code (along with an updated description of your intended design function).  Maybe Gabor and I can pick this problem apart as thoroughly as your previous thread in this forum!
 
-- Bob Elkind

Sorry Bob,  I'll try to explain it a bit better,
1. I have generated a reference clock and that is 50Mhz. There is a 24bit free running counter that counts rising edges of this clock.
 
2. The external clock is the clock to be measure, after receiving 16 rising edges of the external clock I latch the 24bit counter. 
 
module capture(input ref_clk,// 50 MHz refinput in_clk,// freq to be input reset,output reg [23:0] f_meas    );  reg [23:0] count; reg [3:0] presc;  initial begin    f_meas = 0;    presc = 0;// clear prescaler end  // on ref clock rising edge always @ (posedge ref_clk) beginif(reset) begin// synchronous resetcount <= 0;// clear counterend else begincount <= count + 1;//end end  // on ext clock rising edgealways @ (posedge in_clk) beginpresc <= presc + 1;if(presc == 0) beginf_meas <= count;// assign outputendendendmodule 
 

再来一次！
您是否希望寄存器f_meas与ref_clk时钟域或in_clk时钟域对齐？
如果你想让f_meas与ref_clk时钟域对齐，我会给你三次尝试来猜测f_meas寄存器赋值是否属于ref_clk进程或in_clk进程 - 你的前两个猜测将被忽略！
换句话说，你已经知道这个问题的答案了，是吗？
如果您不确定，那么让我们暂时放弃这个设计编码问题，并解决逻辑设计者必须理解的基本概念：
如何识别和正确处理同步逻辑系统的异步输入。
如果f_meas属于ref_clk域，则只需要来自in_clk域的启用信号（或“sample”信号），该信号将转换到ref_clk时钟域。
这需要一个由ref_clk提供时钟的单比特寄存器。
如果您希望对此使能信号执行边沿检测，则需要一个两位寄存器。
如果你提到了in_clk的频率，我就错过了。
如果in_clk的频率高于ref_clk，则必须将使能信号的宽度拉伸至至少一个完整的ref_clk周期。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Here we go again!
 
Do you want register f_meas aligned to ref_clk clock domain or to in_clk clock domain?  If you want f_meas aligned to ref_clk clock domain, I'll give you three tries to guess whether the f_meas register assignment belongs in the ref_clk process or the in_clk process -- and your first two guesses will be ignored!  in other words, you already know the answer to this question, yes?
 
If you are not sure, then let's drop this design coding question for the moment and address the fundamental concept which must be understood by logic designers:
how to recognise and properly handle asynchronous inputs to a synchronous logic system.
 
If f_meas belongs in the ref_clk domain, you simply need an enable signal (or "sample" signal) from the in_clk domain which will cross to the ref_clk clock domain.  This requires a single-bit register clocked by ref_clk.  If you wish to perform edge detection on this enable signal, then you will need a two-bit register.
 
If you mentioned the frequency of in_clk, I missed it.  If in_clk is higher frequency than ref_clk, then the enable signal must be stretched in width to at least one full ref_clk cycle.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

如果in_clk小于ref_clk频率的一半，则另一种设计方法是立即将in_clk输入与ref_clk同步，然后整个设计将驻留在单个时钟域内。
如果您维护两个时钟域，则需要两个BUFG时钟缓冲区。
将in_clk同步到ref_clk会消除in_clk时钟域和其BUFG缓冲区消耗的功率。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

If in_clk is less than half the frequency of ref_clk, an alternative design approach would be to synchronise the in_clk input to ref_clk straight away, and your entire design then dwells within a single clock domain.
 
If you maintain two clock domains, you will need two BUFG clock buffers.  Synchronising in_clk to ref_clk eliminates both the in_clk clock domain and the power consumed by its BUFG buffer.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

eteam00写道：
再来一次！
您是否希望寄存器f_meas与ref_clk时钟域或in_clk时钟域对齐？
如果你想让f_meas与ref_clk时钟域对齐，我会给你三次尝试来猜测f_meas寄存器赋值是否属于ref_clk进程或in_clk进程 - 你的前两个猜测将被忽略！
换句话说，你已经知道这个问题的答案了，是吗？
对不起，我不知道答案。
如果您不确定，那么让我们暂时放弃这个设计编码问题，并解决逻辑设计者必须理解的基本概念：
如何识别和正确处理同步逻辑系统的异步输入。
是的我不太了解异步频率的含义是什么，潜在的缺陷是什么。
以及如何将此异步输入同步到同步逻辑。
如果f_meas属于ref_clk域，则只需要来自in_clk域的启用信号（或“sample”信号），该信号将转换到ref_clk时钟域。
这需要一个由ref_clk提供时钟的单比特寄存器。
如果您希望对此使能信号执行边沿检测，则需要一个两位寄存器。
对不起，我不明白，属于域名是什么意思？
如果你提到了in_clk的频率，我就错过了。
如果in_clk的频率高于ref_clk，则必须将使能信号的宽度拉伸至至少一个完整的ref_clk周期。
In_clk低得多（



以下为原文

eteam00 wrote:
Here we go again!
 
Do you want register f_meas aligned to ref_clk clock domain or to in_clk clock domain?  If you want f_meas aligned to ref_clk clock domain, I'll give you three tries to guess whether the f_meas register assignment belongs in the ref_clk process or the in_clk process -- and your first two guesses will be ignored!  in other words, you already know the answer to this question, yes?
 
Sorry I don't know the answer.
 
If you are not sure, then let's drop this design coding question for the moment and address the fundamental concept which must be understood by logic designers:
how to recognise and properly handle asynchronous inputs to a synchronous logic system.
 
Yes I don't quite comprehend what are the implications of asynchronous frequency, what are the potential pitfalls. And how to synchronize this async input to the sync logic.
 
If f_meas belongs in the ref_clk domain, you simply need an enable signal (or "sample" signal) from the in_clk domain which will cross to the ref_clk clock domain.  This requires a single-bit register clocked by ref_clk.  If you wish to perform edge detection on this enable signal, then you will need a two-bit register.
 
Sorry I don't understand this, What does it mean to belong to a domain?
 
If you mentioned the frequency of in_clk, I missed it.  If in_clk is higher frequency than ref_clk, then the enable signal must be stretched in width to at least one full ref_clk cycle.
 
In_clk much lower (< than 1/60th) than ref_clk
 

 

两个定义：时钟域和异步输入。
时钟域：
所有用单个特定时钟计时的寄存器属于单个时钟域。
所有这些寄存器的输入和输出都有统一的时序参考。
时序参考是时钟。
定时参考应用于寄存器输入，以评估建立和保持时间。
定时参考应用于寄存器输出，以评估最小和最大延迟。
直接或间接源自寄存器输出的逻辑信号也属于同一时钟域。
异步输入：
来自不同或未知时钟域的寄存器输入（直接或间接）被认为是异步输入。
无法确定异步输入的建立和保持时间。
这是异步输入的定义，是识别和区分异步输入的重要特性。
这些定义掩盖了一些细节，并且（因此）小于100％完成，但这两个定义的重要部分如上所述。
在进一步讨论设计实现细节之前，必须理解这两个定义。
遗憾的是，必须在论坛帖子中向您呈现这些概念。
这种材料应该在面对面的对话中呈现（第一次），可以使用图纸和插图，并可以提出问题。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

Two definitions:  clock domain and asynchronous input.
 
Clock domain:
 

• All the registers clocked with a single, specific clock belong to a single clock domain.
  

• All these registers have a uniform timing reference for their inputs and outputs.
  

• The timing reference is the clock.
  

• The timing reference is applied to the register inputs to evaluate setup and hold time.
  

• The timing reference is applied to the register outputs to evaluate minimum and maximum delay.
  

• The logic signals directly or indirectly sourced from the register outputs also belong to the same clock domain.
  

 
Asynchronous input:

• A register input, either direct or indirect, from a different or unknown clock domain is considered an asynchronous input.
  

• The setup and hold time of an asynchronous input cannot be determined.  This is the definition of asynchronous input, the important characteristic which identifies and distinguishes an asynchronous input.
  

 
These definitions gloss over some details, and are (therefore) less than 100% complete,  but the important parts of these two definitions are described above.
 
Before any further discussion of design implementation details, these two definitions must be understood.  It is unfortunate that these concepts must be presented to you in a forum post.  This material should be presented (for the first time) in a face-to-face conversation where drawings and illustrations can be used and questions can be asked.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

鲍勃你好，
我读了你的文章
这个帖子，帖子＃18
这个帖子，帖子＃6
现在它开始变得有意义了。
如果我理解正确，那么异步输入可能会导致合成器不知道的不可预测的传播延迟，因为它没有这些参数，因此电路在某些条件下可能会出现不可预测的行为。
我的问题是
1.当我们可以计算外部频率时，是否可以可靠地建立异步系统的频率计。
2.如果上述情况不可能，那么我应该如何将本质上异步的外部频率转换为FPGA内部运行的同步时钟域？
带着敬意



以下为原文

Hello Bob,
 
I read your articles 
 
this thread, post #18
this thread, post #6
 
and now its starting to make some sense.
 
If I understand correctly then async inputs may cause unpredictable propagation delays that the synthesizer doesn't know about since it doesn't have these parameters with it so the circuit may behave unpredictably under certain conditions.
 
My questions are
 
1. Would it be possible to reliably model an async system for eq a frequency counter when we can count an external frequency.
 
2. If the above is not possible then how should I convert the external frequency which is async in nature to the domain of a sync clock which is running inside the FPGA?
 
With Regards
 
 

我读了你的文章
这个帖子，帖子＃18
这个帖子，帖子＃6
现在它开始变得有意义了。
给它一些时间。
当您花费更多时间处理该问题时，了解时钟域和时钟域交叉将变得更好并且更全面地理解。
如果我理解正确，那么异步输入可能会导致合成器不知道的不可预测的传播延迟，因为它没有这些参数，因此电路在某些条件下可能会出现不可预测的行为。
异步输入不会“导致”甚至影响传播延迟。
它们导致在时钟寄存器的输入处建立和保持时间时序违规。
您是否完全理解数据输入设置时间和数据输入保持时间相对于寄存器时钟的含义？
如果输入到寄存器的数据在发生寄存器时钟（有效）边沿的同时改变状态，则寄存器的状态是不确定的。
为了保证定时寄存器的可靠运行
输入必须在寄存器的时钟沿之前有效且稳定 - 这称为（最小）设置时间
寄存器的时钟沿之后输入必须保持有效且稳定 - 这称为（最小）保持时间
我的问题是
1.当我们可以计算外部频率时，是否可以可靠地建立异步系统的频率计。
请考虑一下您的建模。
你会建模逻辑功能（如果是，然后使用逻辑模拟器）或你是否建模故障率（如果是，然后使用模拟电路模拟器）？
2.如果上述情况不可能，那么我应该如何将本质上异步的外部频率转换为FPGA内部运行的同步时钟域？
外部输入和内部（FPGA）测量系统时钟的频率是多少？
如果外部输入频率小于测量时钟频率的1/2（脉冲宽度比测量时钟周期宽），您在上一篇文章中链接的两个线程详细描述了如何使用异步可靠地执行边沿检测
投入。
如果可以检测到边缘，则可以
在多个测量时钟周期内计算输入边沿
计算输入边缘之间的测量时钟周期
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
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以下为原文

I read your articles 
this thread, post #18
this thread, post #6
and now its starting to make some sense.
 
Give it some time.  Understanding clock domains and clock domain crossing will become better and more fully understood as you spend more time working with the issue.
 
If I understand correctly then async inputs may cause unpredictable propagation delays that the synthesizer doesn't know about since it doesn't have these parameters with it so the circuit may behave unpredictably under certain conditions.
 
Async inputs do not "cause" or even affect propagation delays.  They cause setup and hold time timing violations at inputs to clocked registers.  Do you fully understand the meaning of data input setup time and data input hold time with respect to a register clock?
 
If the data input to a register is changing state at the same time the register clock (active) edge is occurring, the state of the register is uncertain.  In order to guarantee the reliable operation of a clocked register

• The input must be valid and stable before the register's clock edge -- this is called (minimum) setup time
  
• The input must remain valid and stable after the register's clock edge -- this is called (minimum) hold time
  

 My questions are
 
1. Would it be possible to reliably model an async system for eq a frequency counter when we can count an external frequency.
 
Please consider what you would be modeling.  Would you be modeling logic function (if yes, then use a logic simulator) or would you be modeling failure rate (if yes, then use an analogue circuit simulator)?
 
2. If the above is not possible then how should I convert the external frequency which is async in nature to the domain of a sync clock which is running inside the FPGA?
 
What are the frequencies of the external input and the internal (FPGA) measurement system clock?  If the external input frequency is less than 1/2 the measurement clock frequency (with pulse widths which are wider than the measurement clock period), the two threads you linked in your last post describe with considerable detail how to reliably perform edge detection with asynchronous inputs.  If you can detect edges, you can
 

• count input edges over a number of measurement clock cycles
  
• count measurement clock cycles between input edges
  

-- Bob Elkind
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异步输入不会“导致”甚至影响传播延迟。
它们导致在时钟寄存器的输入处建立和保持时间时序违规。
您是否完全理解数据输入设置时间和数据输入保持时间相对于寄存器时钟的含义？
在第一篇论坛帖子中（摘录如下）
“假设最短连接时，封装引脚与寄存器fortiempo和vIncAnterior之间的传播延迟（主要是互连）最短为1nS，而对于最长连接，则为2nS。
如果信号在时钟上升沿之前仅3nS从'0'变为'1'，那么当它们被计时时，所有寄存器都将看到'1'。
如果信号在时钟上升沿之前仅1.5nS从'0'变为'1'，那么一些寄存器在被时钟控制时会看到'1'，因为从封装引脚到寄存器输入的传播延迟很好，
短。
一些寄存器在被计时时会看到'0'，因为从封装引脚到寄存器输入的传播延迟更长。“
你在谈论异步输入如何使电路的功能不稳定。
我在这里读到传播延迟，可能是我误解了它。
如果输入到寄存器的数据在发生寄存器时钟（有效）边沿的同时改变状态，则寄存器的状态是不确定的。
为了保证定时寄存器的可靠运行
输入必须在寄存器的时钟沿之前有效且稳定 - 这称为（最小）设置时间
寄存器的时钟沿之后输入必须保持有效且稳定 - 这称为（最小）保持时间
鲍勃关于设置和保持时间的优秀解释我不知道在设计异步输入时考虑这些的重要性。
请考虑一下您的建模。
你会建模逻辑功能（如果是，然后使用逻辑模拟器）或你是否建模故障率（如果是，然后使用模拟电路模拟器）？
通过模拟电路模拟器，你在谈论SPICE？
外部输入和内部（FPGA）测量系统时钟的频率是多少？
如果外部输入频率小于测量时钟频率的1/2（脉冲宽度比测量时钟周期宽），您在上一篇文章中链接的两个线程详细描述了如何使用异步可靠地执行边沿检测
投入。
如果可以检测到边缘，则可以
在多个测量时钟周期内计算输入边沿
计算输入边缘之间的测量时钟周期
是的，我的asyc输入不到测量系统时钟的一半。
所以我需要将异步输入同步到高频系统时钟。
1.这是通过在系统时钟的每个上升沿测试输入来完成的，并且我发现输入值已经改变了我会考虑是否为正边缘或负边缘？
2.除了将外部时钟与系统时钟同步外，还有其他方法可以设计异步输入系统吗？
3.关于建立和保持时间，如果我设计一个没有异步输入的系统，长路由迹线或多个门单元之间的传播延迟仍然不会违反建立和保持时间。
对不起，我仍然不明白系统如何没有异步输入仍然没有这些？
问候



以下为原文

 Async inputs do not "cause" or even affect propagation delays.  They cause setup and hold time timing violations at inputs to clocked registers.  Do you fully understand the meaning of data input setup time and data input hold time with respect to a register clock?
 
In the first forum post (Excerpt below)
"Let's say the propagation delay (mostly interconnect) between the inc package pin and the registers for tiempo and vIncAnterior is as short as 1nS for the shortest connection and as long as 2nS for the longest connection.
 
If the signal inc changes from '0' to '1' only 3nS before the clock rising edge, then all the registers will see a '1' when they are clocked.  If the signal inc changes from '0' to '1' only 1.5nS before the clock rising edge, then some of the registers will see a '1' when they are clocked, because the propagation delay from inc package pin to register input is nice and short.  Some of the registers will see a '0' when they are clocked, because the propagation delay from inc package pin to register input is longer."
 
you were talking about how an async input can erratic functioning of the circuit. I read about propagation delay here possibly I misuderstood it.
 
 
 
If the data input to a register is changing state at the same time the register clock (active) edge is occurring, the state of the register is uncertain.  In order to guarantee the reliable operation of a clocked register

• The input must be valid and stable before the register's clock edge -- this is called (minimum) setup time
  
• The input must remain valid and stable after the register's clock edge -- this is called (minimum) hold time
  

 
Excellent explanation here Bob regarding the setup and hold time I wasn't aware of the importance of considering these during design with async inputs.
 

Please consider what you would be modeling.  Would you be modeling logic function (if yes, then use a logic simulator) or would you be modeling failure rate (if yes, then use an analogue circuit simulator)?
 
By analogue circuit simulator are you talking about SPICE?
 
What are the frequencies of the external input and the internal (FPGA) measurement system clock?  If the external input frequency is less than 1/2 the measurement clock frequency (with pulse widths which are wider than the measurement clock period), the two threads you linked in your last post describe with considerable detail how to reliably perform edge detection with asynchronous inputs.  If you can detect edges, you can
 

• count input edges over a number of measurement clock cycles
  
• count measurement clock cycles between input edges
  

Yes my asyc input is less than half the measurement system clock.
So I would need to synchonize the async input to the high frequency system clock.


1. Is this done by testing the input at every rising edge of the system clock and incase I find that the value of the input has changed I would consider if either as a positive or negative edge?
2. Apart from synchronizing the external clock to the system clock is there any other approach to design a async input system?
3. Regarding setup and hold time, If I design a system with no async inputs, won't the setup and hold times still be violated by propogation delays between long routed traces or multiple gate units.
Sorry I still don't understand how a system void of async inputs still would be free of these?


Regards