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嗨,
我有一个4时钟域的原始设计。 在添加第5个时钟域并将设计加载到芯片中后,该设计在硬件中不再起作用。 我正在使用斯巴达3E 1600 这是一个很大的设计,但作为一个例子,我有一个简单的计数器,如下所示: ----进程闪烁LED - blinking_led:进程开始等到rising_edge(hkbClk); if(ledCount_hkb = LED_tiME)然后ledCount_hkb'0'); - 重置为0 s_FPGAStatus else ledCount_hkb end if; end process blinking_led; 即使这停止了工作。 s_fpgaStatus不再切换。 我将所有的时钟用管道输送到我板上的测试点,所有的时钟似乎运行正常,所以我真的很困惑。 我的时钟频率(MHz)分别为27,28,40,108 新的时钟频率设置为200,但我确实尝试将它一直减少到100以确定它是否解决了问题但事实并非如此。 我想知道是否有人之前见过这个。 谢谢 阿米什 以上来自于谷歌翻译 以下为原文 Hi, I had an original design with 4 clock domain. Upon adding a 5th clock domain and loading the design into the chip, the design does not work anymore in hardware. I am using spartan 3E 1600 It's a big design but as an example, I had a simple counter as shown below: -- -- Process to blink LED -- blinking_led : process begin wait until rising_edge(hkbClk); if(ledCount_hkb = LED_TIME) then ledCount_hkb <= (others => '0'); -- Reset to 0 s_fpgaStatus <= NOT s_fpgaStatus; -- Invert led output else ledCount_hkb <= ledCount_hkb + 1; -- Increment by 1 end if; end process blinking_led; Even this stopped working. s_fpgaStatus does not toggle anymore. I piped all the clocks to test points on my board and all the clocks seems to be running fine so I am really puzzled as what is happening. My clock frequency (MHz) were 27, 28, 40, 108 The new clock frequency was set to 200 but I did try to decrease it all the way to 100 to see if it fixes the issue and it did not. I was wondering if anybody has seen this before. Thanks Amish |
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7个回答
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在整个实施过程的综合,翻译,制图,布局和时序分析阶段,您获得了哪些错误和警告?
----------------------------是的,我这样做是为了谋生。 以上来自于谷歌翻译 以下为原文 What errors and warnings were you getting throughout the synthesis, translation, mapping, placement and timing-analysis phases of the implementation process? ----------------------------Yes, I do this for a living. |
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“旧”和“新”设计是否在模拟中按预期工作?您使用的ISE版本是什么?
------------------------------------------“如果它不起作用 模拟,它不会在板上工作。“ 以上来自于谷歌翻译 以下为原文 Do the 'old' and 'new' designs both work as expected in simulation? What version of ISE are you using? ------------------------------------------ "If it don't work in simulation, it won't work on the board." |
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我正在使用planahead 13.4
工具未显示重大错误或警告。 我查看了综合报告,翻译地图和标准杆,没有什么能像我一样跳到我身边。 以上来自于谷歌翻译 以下为原文 I am using planahead 13.4 No significant error or warning indicated by the tool. I looked at the report for synthesis, translate map and par, There was nothing that jumped at me as being weird. |
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您是否为时钟设置了PERIOD约束?
以上来自于谷歌翻译 以下为原文 Do you have PERIOD constraints set for your clocks? |
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那么在模拟中呢?顺便说一下,如果你没有做模拟,你真的应该是!
------------------------------------------“如果它不起作用 模拟,它不会在板上工作。“ 以上来自于谷歌翻译 以下为原文 And what about in simulation? BTW, if you aren't doing simulations, you REALLY should be! ------------------------------------------ "If it don't work in simulation, it won't work on the board." |
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时钟约束设置正确。
我在标准杆之后做了计时模拟,一切看起来都很好 它不会让我压缩整个项目所以我附上了代码 两者之间的唯一区别在于sn_top_not.vhd和sn_top.vhd的第374行和第404行。 clockIssueSource.zip 36 KB 以上来自于谷歌翻译 以下为原文 Clock constraint are set properly. I did timing simulation after par and everything looks good. It won't let me zip the full project so I attached the code instead The only difference between the two is on line 374 and 404 of sn_top_not.vhd and sn_top.vhd. clockIssueSource.zip 36 KB |
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管理将所有内容全部添加到1个zip文件中,并设置完整路径
clockIssue.zip 122 KB 以上来自于谷歌翻译 以下为原文 Manage to add everything alltogether into 1 zip file with full path setup clockIssue.zip 122 KB |
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