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[问答] SPC56EL60L3闪存阵列完整性检查无法工作
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您好,我正在使用SPC56EL60L3和SPC5STUDIO v5.0。
我需要实现闪存阵列完整性检查,作为开机自检程序的一部分。
我从ST应用程序工程中获得了一些示例代码,但我无法使其工作。
奇怪的是,如果我尝试在调试模式下运行代码,它可以工作..当我尝试在debig模式之外运行它时,我得到一个未处理的异常。
请在下面找到我的代码(我对ST应用工程师提供的代码稍作修改)。

/ *闪存阵列完整性测试* /
#define PAR_CFLASH_MISR0 0xBFC5FC60
#define PAR_CFLASH_MISR1 0x2D32A870
#define PAR_CFLASH_MISR2 0xDAF09F36
#define PAR_CFLASH_MISR3 0xC0DB86FF
#define PAR_CFLASH_MISR4 0x00016014

#define FLASH_PSW 0xF9F99999

#define UT0_UTE 0x80000000U
#define UT0_AID 0x00000001U
#define UT0_AIE 0x00000002U
#define UT0_AIS 0x00000004U


static int32_t CoreFlashIntegrityTest(void)
{
int32_t retVal_i32 = CORE_TEST_ERROR;
int8_t misrErrCounter_i8 = 0;

CFLASH.UT0.R = FLASH_PSW;

while((CFLASH.UT0.R& UT0_UTE)== 0);

CFLASH.HBS.R = 0x000003FF;
CFLASH.UT0.R& =〜(UT0_AIS); / *默认值为零* /

/ *使MISR UM0通过UM4播种所需的值。* /
CFLASH.UMISR [0] .R = 0U;
CFLASH.UMISR [1] .R = 0U;
CFLASH.UMISR [2] .R = 0U;
CFLASH.UMISR [3] .R = 0U;
CFLASH.UMISR [4] .R = 0U;

/ *数组完整性启用* /
CFLASH.UT0.R | = UT0_AIE;

while((CFLASH.UT0.R& UT0_AID)== 0);

misrErrCounter_i8 + = REGS_COMP(CFLASH.UMISR [0] .R,PAR_CFLASH_MISR0);
misrErrCounter_i8 + = REGS_COMP(CFLASH.UMISR [1] .R,PAR_CFLASH_MISR1);
misrErrCounter_i8 + = REGS_COMP(CFLASH.UMISR [2] .R,PAR_CFLASH_MISR2);
misrErrCounter_i8 + = REGS_COMP(CFLASH.UMISR [3] .R,PAR_CFLASH_MISR3);
misrErrCounter_i8 + = REGS_COMP(CFLASH.UMISR [4] .R,PAR_CFLASH_MISR4);

CFLASH.UT0.R& =〜(UT0_AIE);

IF(misrErrCounter_i8 == 0)
{
retVal_i32 = CORE_TEST_OK;
}

return retVal_i32;
}

此外,我有以下问题:

- HBS设置:如何配置HBS。看起来它用于选择我想要运行测试的闪存扇区。如何将所需扇区与寄存器值相关联?
- 在示例代码中,MISR [0:4 [寄存器初始化为0.为什么?是0,总是正确的价值?
- 在示例代码中,MISR [0:4]寄存器与测试结束时的某些预期值进行比较。如何确定预期值?这些固定值是什么?


谢谢。
问候
亚历山德罗

以上来自于谷歌翻译


以下为原文




Hello, I'm working with SPC56EL60L3 and SPC5STUDIO v5.0.
I need to implement flash array integrity check,as part of the power on self test procedure.
I got some sample code from ST application engineering, but I can't get it to work.
The odd thing is that, if I try to run the code in debug mode, it works.. When I try to run it outside of the debig mode, I get an unhandLED exception.
Please find my code below (I made some little changes to the code provided by ST application engineer).


/* flash array integrity test */
#define PAR_CFLASH_MISR0 0xBFC5FC60
#define PAR_CFLASH_MISR1 0x2D32A870
#define PAR_CFLASH_MISR2 0xDAF09F36
#define PAR_CFLASH_MISR3 0xC0DB86FF
#define PAR_CFLASH_MISR4 0x00016014

#define FLASH_PSW 0xF9F99999

#define UT0_UTE 0x80000000U
#define UT0_AID 0x00000001U
#define UT0_AIE 0x00000002U
#define UT0_AIS 0x00000004U


static int32_t CoreFlashIntegrityTest( void )
{
int32_t retVal_i32 = CORE_TEST_ERROR;
int8_t misrErrCounter_i8 = 0;

CFLASH.UT0.R = FLASH_PSW;

while( ( CFLASH.UT0.R & UT0_UTE ) == 0);

CFLASH.HBS.R = 0x000003FF;
CFLASH.UT0.R &= ~( UT0_AIS ); /* Default value is zero*/

/* Seed the MISR UM0 thru UM4 with desired values.*/
CFLASH.UMISR[0].R = 0U;
CFLASH.UMISR[1].R = 0U;
CFLASH.UMISR[2].R = 0U;
CFLASH.UMISR[3].R = 0U;
CFLASH.UMISR[4].R = 0U;

/* Array Integrity Enable */
CFLASH.UT0.R |= UT0_AIE;

while( ( CFLASH.UT0.R & UT0_AID ) == 0 );

misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[0].R, PAR_CFLASH_MISR0 );
misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[1].R, PAR_CFLASH_MISR1 );
misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[2].R, PAR_CFLASH_MISR2 );
misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[3].R, PAR_CFLASH_MISR3 );
misrErrCounter_i8 += REGS_COMP( CFLASH.UMISR[4].R, PAR_CFLASH_MISR4 );

CFLASH.UT0.R &= ~( UT0_AIE );

if ( misrErrCounter_i8 == 0 )
{
retVal_i32 = CORE_TEST_OK;
}

return retVal_i32;
}

Furthermore I have the following questions:

- HBS setting: how do I configure HBS. It looks like it's used for selecting the flash sectors on which I want to run the test. How do I relate the desired sector to the register value?
- In the sample code the MISR[0:4[ registers are initialized to 0. Why is that? Is 0, always the right value?
- In the sample code, the MISR[0:4] registers are compared to some expected values at the end of the test. How do I determine the expected values? Are those fixed values?


Thank you.
Regards
Alessandro
0
2019-5-24 10:46:55   评论 分享淘帖 邀请回答
4个回答
你好,
在ST提供的示例代码中,我注意到一个指令让我觉得可能需要从RAM运行flash完整性例程:
 
#pragma ghs section text ='。ram_code'
 
这是放在函数的开头。
在函数结束时我发现了这个:
 
#pragma ghs section text ='default'
 
所以,现在还有另一个问题:我是否需要从RAM运行此代码?
谢谢。
问候
亚历山德罗

以上来自于谷歌翻译


以下为原文




Hello,
in the sample code provided by ST, I noticed a directive which made me think the flash integrity routine may need to be run from RAM:


#pragma ghs section text='.ram_code'

This is placed at the beginning of the function.
At the end of the function I found this:

#pragma ghs section text='default'

So, now there is another question: do I need to run this code from RAM?
Thank you.
Regards
Alessandro
2019-5-24 10:58:16 评论

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亚历山德罗你好,
HBS寄存器功能如Leopard参考手册的表287所示。
表292中描述了MISR寄存器。豹子参考手册的UM0字段描述。
 通过写入MISR寄存器,可以将MISR加到任何值。
 在AIC的末尾,MISR [0:4]寄存器与依赖于所选扇区及其内容的预期值进行比较。
问候

以上来自于谷歌翻译


以下为原文




Hello Alessandro,

HBS register functions are shown in TABLE 287 of Leopard Reference Manual.
MISR register is described in Table 292. UM0 field descriptions of Leopard reference manual.
   The MISR can be seeded to any value by writing the MISR registers.

   A the end of the AIC, MISR[0:4] registers are compared to the expected values that depend on the selected sectors and their content.

Regards
2019-5-24 11:31:44 评论

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你好Mosè,
谢谢您的回复。
HBS和LMS寄存器在用户手册中描述(表293描述了LMS寄存器,表294描述了HBS)。
我的应用程序使用闪存的扇区2,3,4(低地址空间的L2,L3和L4)和6(中等地址空间的M0)。
所以我按如下方式配置寄存器:
CFLASH.HBS.R = 0x00000000; / *没有使用高地址空间的扇区* /
 
 CFLASH.LMS.R = 0x0001001C; / * L2,L3,L4和M0用于* /这是正确的吗?
还有一个问题与MISR寄存器功能有关。
我在第24.1.5.12.1节中阅读了表299,但我仍然不知道它是如何工作的..
问题是:在完整性检查后,如何确定要与MISR寄存器内容进行比较的预期值?
在我的代码中,在运行测试之前,MISR寄存器被初始化为0。
谢谢。
问候。
亚历山德罗

以上来自于谷歌翻译


以下为原文




Hello Mosè,
thank you for your reply.
HBS and LMS registers are described in the user manual (table 293 describes the LMS register and table 294 describes HBS).
My application is using sectors 2,3,4 (L2, L3 and L4 of low address space) and 6 (M0 of the medium address space) of the flash memory.
So i configued the registers as follows:
CFLASH.HBS.R = 0x00000000; /* none of the sectors in high address space is used */

CFLASH.LMS.R = 0x0001001C; /*L2, L3, L4 and M0 are used */Is this correct?
One more question is related to the MISR registers functionality..
I read table 299 in section 24.1.5.12.1, but I still don't get how it works..
The question is: how do I determine the expected value to be compared to the content of the MISR registers after the integrity check?
In my code, the MISR registers are initialized to 0, before running the test.
Thank you.
Regards.
Alessandro
2019-5-24 12:03:37 评论

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亚历山德罗你好,
根据你的描述CFLASH.LMS.R设置是正确的。
您可以按照“经验”方法在阵列完整性检查后查找签名的预期值:
闪存微,运行数组完整性检查,在计算结束时(没有任何错误)MISR寄存器将包含您搜索的值。
如果L2,L3,L4和M0扇区的内容不会改变,您可以将此值用作预期值。
最好的祝福,
Mosè地区

以上来自于谷歌翻译


以下为原文




Hello Alessandro,
According to your description CFLASH.LMS.R set is correct.
You can follow an 'empiric' method to find the expected values of the signature after array integrity check:
Flash the micro, run the array integrity check, at the end of the calculation (without any error)  the MISR registers will contain the value you search for.
If the content of L2, L3, L4 and M0 sectors won't change, you can use this value as the expected one.
Best regards,
Mosè
2019-5-24 12:09:59 评论

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