软件如何控制实际的FPGA布线

实施工具负责此流程
检查这些教程
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug904-vivado-implementation.pdf
http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_fpga_design_flow_overview.htm
谢谢和RegardsBalkrishan -----------------------------------------------
---------------------------------------------请将帖子标记为
一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。



以下为原文

Implementation tool take care for this flow
check these tutorials
 
http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_2/ug904-vivado-implementation.pdf
 
http://www.xilinx.com/itp/xilinx10/isehelp/ise_c_fpga_design_flow_overview.htm
Thanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

它并没有真正回答我的问题。
让我们说在软件中，布线由int（整数）表示，但不包含电线的真实物理方面。
物理FPGA的特定网络或线路如何在软件中采用特定的形状，它只用int（整数类型）表示？



以下为原文

it doesn't really answer my question.
 
Let's say in software the wiring is represented by the int  (integer), but that doesn't contain the real physcial aspect of the wire. 
 
How can a physical FPGA 's particular net or wire takes a particular shape when in software it's only represented by a int (integer type)?

合成过程从hdl代码转换为逻辑http://people.sabanciuniv.edu/erkays/el310/SimSyn_03.pdfhttp://www.utdallas.edu/~zxb107020/EE6306/Tutorial/VHDL.pdf
谢谢和RegardsBalkrishan -----------------------------------------------
---------------------------------------------请将帖子标记为
一个答案“接受为解决方案”，以防它有助于解决您的查询。如果一个帖子引导到解决方案，请给予赞誉。



以下为原文

conversion from hdl code to logic done by synthesis process

http://people.sabanciuniv.edu/erkays/el310/SimSyn_03.pdf

http://www.utdallas.edu/~zxb107020/EE6306/Tutorial/VHDL.pdfThanks and Regards
Balkrishan
--------------------------------------------------------------------------------------------
Please mark the post as an answer "Accept as solution" in case it helped resolve your query.
Give kudos in case a post in case it guided to the solution.

@lilzz
在RTL中定义逻辑后，综合工具会将描述转换为网表（单元格，网络......）。
生成的网表将由实现工具使用，MAP和PAR（ISE）将基于结构上的可用资源完成。
请参阅以下链接：
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_implement_fpga_design.htm
谢谢，Anusheel -----------------------------------------------
-  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  -  - 搜索
在论坛上发布查询之前，与您的设备和工具相关的文档/答案记录。搜索相关论坛并确保您的查询不会重复。请将帖子标记为“接受为解决方案”，以防它有助于解决您的查询。帮助
回答 - >给予Kudos ---------------------------------------------
--------------------------------------------------



以下为原文

@lilzz
 
Once you define the logic in RTL, synthesis tool will convert the description into a netlist (cells, nets...).
Generated netlist will be used by an implementation tool, MAP and PAR (ISE) will be done on the basis of available resources on the fabric. Refer below link:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/ise_c_implement_fpga_design.htm
 
Thanks,
Anusheel
-----------------------------------------------------------------------------------------------
Search for documents/answer records related to your device and tool before posting query on forums.
Search related forums and make sure your query is not repeated.

Please mark the post as an answer "Accept as solution" in case it helps to resolve your query.
Helpful answer -> Give Kudos
-----------------------------------------------------------------------------------------------

对不起，我没有说清楚。
我不是在谈论C代码中的设计。
我实际上正在研究有关MAP，placen-route工具源代码的详细信息，它是C代码。
我在这些工具中看到，网络由int（整数类型）表示。



以下为原文

Sorry, I didn;t make it clear.
 
I am not talking about the design in C code.
 
I am actually studying in details about the MAP, placen-route tool source code which is in C code. 
 
I saw in those tools, the nets are represented by int (integer type).
 
 

您可以将FPGA表示为图形，其中顶点表示LUT或DFF，其中边表示路由。
有了这个，假设您可以合成设计并从RTL获得所需的门和连接，则映射器的任务是将合成图中的顶点分配给fpga图中的顶点，并且路由器的任务是查找
有效的连接没有重叠。
映射设计与合成图具有相同的连通性（即边缘），但fpga图具有从顶点到顶点的许多可能边，并且可以跳过多个顶点以从一个节点到另一个节点。
路由器必须找到从合成边缘列表到fpga边缘列表的低成本映射。对于映射器和路由器，在时序和时间方面都存在与fpga图中使用的每个边缘相关的成本。
功率。
因此映射＆amp;
路由（最有可能）是图操作的凸优化问题。
- 如果提供的信息有用，请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。



以下为原文

You can represent the FPGA as a graph where the vertices represent LUTs or DFFs and where edges represent the routing. With this, assuming you can synthesize the design and get the gates and connectivity you need from the RTL, the task of the mapper is assigning the vertices in the synthesis graph to the vertices in the fpga graph and the task of the router is to find efficient connections without overlaps. The mapped design has the same connectivity (ie edges) as the synthesis graph but the fpga graph has many possible edges from vertex to vertex and one can jump over multiple vertices to get from one node to another. The router has to find low cost mapping from the synthesis edge list to fpga edge list.
For both mapper and router, there is a cost associated with each edge used in the fpga graph both in terms of timing & power. So mapping & routing is (most probably) a convex optimization problem of graph manipulation.
- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.

lilzz写道：
对不起，我没有说清楚。
我不是在谈论C代码中的设计。
我实际上正在研究有关MAP，placen-route工具源代码的详细信息，它是C代码。
我在这些工具中看到，网络由int（整数类型）表示。
在计算机世界中，任何东西都可以用1和0表示。
你试图重新发明轮子还是什么？
...似乎您可能需要进一步回顾FPGA历史的旧日
正如其他人所指出的那样，FPGA的名字就是“现场可编程门阵列”器件，FPGA本身已经有了逻辑，盒子，开关，wrires等阵列......它们已经准备好连接成有用的电路
现在来到有趣的部分如何构建您的电路，在过去的日子里我们仍然使用orcad原理图作为设计输入工具来告诉FPGA如何连接那些电线，LUT ......以及其他人甚至挖掘芯片来做手册
路由（幸运的是我没有），....当然有一个非常好的引擎可以将设计输入表格翻译成设备可以理解或可配置的格式，因为我记得Xilinx称之为M1引擎，不知道他们有什么
在那之前



以下为原文

lilzz wrote:
Sorry, I didn;t make it clear.
 
I am not talking about the design in C code.
 
I am actually studying in details about the MAP, placen-route tool source code which is in C code. 
 
I saw in those tools, the nets are represented by int (integer type).
 
 

In the computer world anything can be represented by 1s and 0s , period.
 
Do you try to reinvent the wheel or what ?  ... it seems you may need to look further back into the old day of FPGA history
 
Like other has pointed out, the FPGA as its name suggested is the "field programmable gate array" device,  the FPGA by itself already had the arrays of  logics,  boxes, switches, wrires ... those are ready to be connected into useful circuits
 
Now come the fun part how to build your circuit, back in the old day we still using orcad schematic as design entry tool to tell the FPGA how to connect those wire, LUTs ...and others even digged in the chip to do the manual routing (luckily  me not), .... of course there is an ingenious engine behind to  translate the design entry form into the format the device can understand, or configurable, as I recall Xilinx call it the  M1 engine, not sure what they had before that