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` 本帖最后由 我还能怎样 于 2019-4-10 15:17 编辑 小弟毕设是用DSP28335做有源降噪，现在在AIC23的Line in输入口输入一个单频声之后，Line out输出的声听起来总有嘟嘟嘟的噪声，不知道是为什么。主程序代码如下。希望有大神解答一下。 #include <time.h> #include #include "math.h" #include #include #include "LMS.h" #include "DSP2833x_Device.h" // DSP2833x Headerfile Include File #include "DSP2833x_Examples.h" // DSP2833x Examples Include File extern void InitMcbspGpio(void); #define PI 3.141592654 #define Fs 5000 #define Ts 1/Fs //采样频率 #define F3 10 #define NUM_OF_POINT 512 // AIC23_DSP_SPI_control.c External Function Prototypes //extern void init_mcbsp_spi(); //extern void mcbsp_xmit (int a); //extern void aic23_init(int mic, int i2s_mode); // Prototype statements for functions found within this file. void init_dma(void); void init_mcbspa(void); interrupt void local_D_INTCH1_ISR(void); // Channel 1 Rx ISR interrupt void local_D_INTCH2_ISR(void); // Channel 2 Tx ISR //=============================================================== // SELECT AUDIO INPUT AND DIGITAL AUDIO INTERFACE OPTIONS HERE: //=============================================================== Uint16 AIC23Write(int Address,int Data); void I2CA_Init(void); void Delay(int time); void delay(); // AIC23_DSP_SPI_control.c External Function Prototypes // 2 buffers, PING & PONG are used. When PING is being filled up, PONG data is processed and vice versa. // L & R channel data is stored contigously in PING. Likewise in PONG. // In both buffers, First 512 32-bit locations are L-channel data. Next 512 32-bit locations are R-channel data. #pragma DATA_SECTION (ping_buffer, "DMARAML5"); // Place ping and pong in DMA RAM L5 #pragma DATA_SECTION (pong_buffer, "DMARAML5"); #pragma DATA_SECTION (out1, "DMARAML5"); // Place ping and pong in DMA RAM L5 #pragma DATA_SECTION (out2, "DMARAML5"); Uint32 out1[512]; // Note that Uint32 is used, not Uint16 Uint32 out2[512]; Uint32 ping_buffer[512]; // Note that Uint32 is used, not Uint16 Uint32 pong_buffer[512]; Uint32 * L_channel = &ping_buffer[0]; // This pointer points to the beginning of the L-C data in either of the buffers Uint32 * R_channel = &ping_buffer[256]; // This pointer points to the beginning of the R-C data in either of the buffers Uint32 ping_buff_offset = (Uint32) &ping_buffer[0]; Uint32 pong_buff_offset = (Uint32) &pong_buffer[0]; Uint32 out1_offset = (Uint32) &out1[0]; Uint32 out2_offset = (Uint32) &out2[0]; Uint16 first_interrupt = 1; // 1 indicates first interrupt Uint32 k = 0; int i, j; //#pragma DATA_SECTION(noise, ".X"); int noise[NUM_OF_POINT]; //#pragma DATA_SECTION(out_error, ".X"); int out_error[NUM_OF_POINT]; //#pragma DATA_SECTION(out_error2, ".X");// //float out_error2[NUM_OF_POINT];// //#pragma DATA_SECTION(out_y, ".X"); int out_y[512]; //#pragma DATA_SECTION(out_y2, ".X");// //float out_y2[NUM_OF_POINT];// void main(void) { EALLOW; // Step 1. Initialize System Control: // PLL, WatchDog, enable Peripheral Clocks InitSysCtrl(); // Step 2. Initalize GPIO: // For this example, enable the GPIO PINS for McBSP operation. InitMcbspGpio(); InitI2CGpio(); /* Fill the buffer with dummy data */ for(k=0; k<1024; k++) { ping_buffer[k] = 0x00000000; } for(k=0; k<1024; k++) { pong_buffer[k] = 0x00000000; } for(k=0; k<1024; k++) { out1[k] = 0x00000000; } for(k=0; k<1024; k++) { out2[k] = 0x00000000; } // Step 3. Clear all interrupts and initialize PIE vector table: // Disable CPU interrupts DINT; // Initialize PIE control registers to their default state. // The default state is all PIE interrupts disabled and flags // are cleared. // This function is found in the DSP2833x_PieCtrl.c file. InitPieCtrl(); EALLOW; DINT; // Disable interrupts again (for now) // Disable CPU interrupts and clear all CPU interrupt flags: IER = 0x0000; IFR = 0x0000; // Step 4. Initialize the Peripherals ping_buff_offset++; // Start at location 1 (32-bit r/w from loc. 1, then 0) pong_buff_offset++; // Start at location 1 (32-bit r/w from loc. 1, then 0) //init_mcbsp_spi(); // Initialize McBSP-B as SPI Control out1_offset++; // Start at location 1 (32-bit r/w from loc. 1, then 0) out2_offset++; // Start at location 1 (32-bit r/w from loc. 1, then 0) I2CA_Init(); AIC23Write(0x00,0x1f);//左声道输入音量 Delay(100); AIC23Write(0x02,0x1f);//右声道输入音量 Delay(100); AIC23Write(0x04,0xBf);//左声道输出音量 Delay(100); AIC23Write(0x06,0xBf);//右声道输出音量 Delay(100); AIC23Write(0x08,0x12);//DAC选择，lin输入//AIC23Write(0x08,0x14);//DAC选择，MIC输入 Delay(100); AIC23Write(0x0A,0x00); Delay(100); AIC23Write(0x0C,0x00); Delay(100); AIC23Write(0x0E,0x43);//AIC23Write(0x0E,0x43);//数字音频接口格式控制，AIC23主模式，dsp初始化，转换比特值设定00即：16bit--》96dB Delay(100); AIC23Write(0x10,0x23);//AIC23Write(0x10,0x23);//设置采样率为16khz；USB模式下时钟为12mhz，采样率为12/272=44.1Khz Delay(100); AIC23Write(0x12,0x01);//激活标志 Delay(100); //AIC23Init init_dma(); // Initialize the DMA before McBSP, so that DMA is ready to transfer the McBSP data InitMcbspa();//init_mcbspa(); // Initalize McBSP-A //init_zone7(); //InitMcbspa(); //init_mcbspa(); // Initalize McBSP-A delay_loop(); EALLOW; DmaRegs.CH1.CONTROL.bit.RUN = 1; // Start rx on Channel 1 /* Reassign ISRS */ PieVectTable.DINTCH1 = &local_D_INTCH1_ISR; PieVectTable.DINTCH2 = &local_D_INTCH2_ISR; /* Configure PIE interrupts */ PieCtrlRegs.PIECTRL.bit.ENPIE = 1; // Enable vector fetching from PIE block PieCtrlRegs.PIEACK.all = 0xFFFF; // Enables PIE to drive a pulse into the CPU // The interrupt can be asserted in the following interrupt lines PieCtrlRegs.PIEIER7.bit.INTx1 = 1; // Enable INTx.1 of INT7 (DMA CH1) PieCtrlRegs.PIEIER7.bit.INTx2 = 1; // Enable INTx.2 of INT7 (DMA CH2) /* Configure system interrupts */ IER |= 0x0040; // Enable INT7 EINT; // Global enable of interrupts EDIS; /* Wait for data */ while(1) { for(i=0;i<256;i++) { noise=(int)ping_buffer; noise[i+256]=(int)pong_buffer; out_error=(int)ping_buffer[i+256]; out_error[i+256]=(int)pong_buffer[i+256]; } for(i=0;i<512;i++) { if(i { for(j=0;j<=i;j++) { lms_x[j] =noise[i-j]; lms_error[j]=out_error[i-j]; } } else { for(j=0;j { lms_x[j] = noise[i-j]; lms_error[j]=out_error[i-j]; } } lms_param_in.d = noise;//signal_noise; lms_param_in.error = &lms_error[0]; lms_param_in.x_ptr = &lms_x[0]; lms_param_in.length_x = LMS_M; LMS_Gradient_Instantaneous_Estimates(&lms_param_in, &lms_param_out); //运行瞬时梯度估计LMS算法 耗时514个时钟周期 out_y =lms_param_out.y;// //Delay(10); //out_y =noise; } for(i=0;i<256;i++) { out1=out_y; //输出左通道 out1[i+256]=out_y; //输出右通道 out2=out_y[i+256]; //输出左通道 out2[i+256]=out_y[i+256];//输出右通道 } }//while }//main // INT7.1 - interrupt void local_D_INTCH1_ISR(void) // DMA Ch1 - McBSP-A Rx { EALLOW; if(first_interrupt==1) // No processing needs to be done (B/c interrupt occurs { // at beginning of DMA transfers to ping buffer - no data received yet) first_interrupt=0; // Turn flag off and exit interrupt } else { DmaRegs.CH2.CONTROL.bit.RUN = 1; } // When DMA first starts working on ping buffer, set the shadow registers // to start at pong buffer next time and vice versa if( DmaRegs.CH1.DST_ADDR_SHADOW == ping_buff_offset) { DmaRegs.CH1.DST_ADDR_SHADOW = pong_buff_offset; DmaRegs.CH1.DST_BEG_ADDR_SHADOW = pong_buff_offset; } else { DmaRegs.CH1.DST_ADDR_SHADOW = ping_buff_offset; DmaRegs.CH1.DST_BEG_ADDR_SHADOW = ping_buff_offset; } /*for(i=0;i<512;i++) { //Delay(0.2); out1=ping_buffer; out2=pong_buffer; }*/ // To receive more interrupts from this PIE group, acknowledge this interrupt PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; EDIS; } // INT7.2 interrupt void local_D_INTCH2_ISR(void) // DMA Ch2 - McBSP-A Tx { // When DMA first starts working on ping buffer, set the shadow registers // to start at pong buffer next time and vice versa EALLOW; if(DmaRegs.CH2.SRC_ADDR_SHADOW == out1_offset)// { DmaRegs.CH2.SRC_ADDR_SHADOW = out2_offset;// DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = out2_offset;//(Uint32)&out_y[0]; } else { DmaRegs.CH2.SRC_ADDR_SHADOW =out1_offset;//pong_buff_offset;//(Uint32)&out_y[0]; DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = out1_offset;//pong_buff_offset;//(Uint32)&out_y[0]; } PieCtrlRegs.PIEACK.all = PIEACK_GROUP7; // To receive more interrupts from this PIE group, acknowledge this interrupt EDIS; } void init_dma() { EALLOW; DmaRegs.DMACTRL.bit.HARDRESET = 1; asm(" NOP"); DmaRegs.PRIORITYCTRL1.bit.CH1PRIORITY = 0; /* DMA Channel 1 - McBSP-A Receive */ DmaRegs.CH1.BURST_SIZE.all = 1; // 2 16-bit words/burst (1 32-bit word) - memory address bumped up by 1 internally DmaRegs.CH1.SRC_BURST_STEP = 1; // DRR2 must be read first & then DRR1. Increment by 1. Hence a value of +1. (This is a 2's C #) DmaRegs.CH1.DST_BURST_STEP = -1; // Copy DRR2 data to address N+1 and DRR1 data to N. Hence -1 (32-bit read= read addr N+1 as MSB, then N as LSB) DmaRegs.CH1.TRANSFER_SIZE = 511; // DMA Interrupt every 1024 (n+1) bursts (1024 32-bit words). DmaRegs.CH1.SRC_TRANSFER_STEP = -1; // Decrement source address by 1 (from DRR1 back to DRR2) after processing a burst of data DmaRegs.CH1.DST_TRANSFER_STEP = 513; // After copying 1 32-bit word of L-C data (1 burst), move down to R-C data in a given buffer DmaRegs.CH1.SRC_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR2.all; // First read from DRR2 DmaRegs.CH1.SRC_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DRR2.all; DmaRegs.CH1.DST_ADDR_SHADOW = ping_buff_offset; // First write to ping_buffer[1] DmaRegs.CH1.DST_BEG_ADDR_SHADOW = ping_buff_offset; DmaRegs.CH1.DST_WRAP_SIZE = 1; // After LEFT(1) and then RIGHT(2), go back to LEFT buffer DmaRegs.CH1.SRC_WRAP_SIZE = 0xFFFF; // Arbitary large value. We'll never hit this..... DmaRegs.CH1.DST_WRAP_STEP = 2; // From starting address, move down 2 16-bit addresses to write nxt 32-bit word DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; DmaRegs.CH1.MODE.bit.CHINTE = 1; // Enable DMA channel interrupts DmaRegs.CH1.MODE.bit.CHINTMODE = 0; // Interrupt at beginning of transfer DmaRegs.CH1.MODE.bit.PERINTSEL = 15; // McBSP MREVTA DmaRegs.CH1.MODE.bit.CONTINUOUS = 1; // Enable continuous mode (continuously receives)// Enable interrupts from peripheral (to trigger DMA) DmaRegs.CH1.MODE.bit.PERINTE = 1; // Enable interrupts from peripheral (to trigger DMA) /* DMA Channel 2 - McBSP-A Transmit */ DmaRegs.CH2.BURST_SIZE.all = 1; // 2 16-bit words/burst (1 32-bit word) - value bumped up by 1 internally DmaRegs.CH2.SRC_BURST_STEP = -1; // Copy data at address N+1 to DXR2 first then data at N to DXR1. Hence -1 DmaRegs.CH2.DST_BURST_STEP = 1; // DXR2 must be written to first & then DXR1. Increment by 1. Hence a value of +1. (This is a 2's C #) DmaRegs.CH2.TRANSFER_SIZE = 511; // DMA Interrupt every 1024 (n+1) 16-bit words. McBSP still handles 16-bit data only in registers DmaRegs.CH2.SRC_TRANSFER_STEP =513; // After copying 1 32-bit word L-C data, move down to R-C data in a given buffer DmaRegs.CH2.DST_TRANSFER_STEP = -1; // Decrement dest. address by 1 (DXR1 back to DXR2) after processing a burst of data DmaRegs.CH2.SRC_ADDR_SHADOW = out1_offset;//; // First read from ping_buffer[1] DmaRegs.CH2.SRC_BEG_ADDR_SHADOW = out1_offset;//; DmaRegs.CH2.DST_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR2.all; // First write to DXR2 DmaRegs.CH2.DST_BEG_ADDR_SHADOW = (Uint32) &McbspaRegs.DXR2.all; DmaRegs.CH2.SRC_WRAP_SIZE = 1; // After LEFT(1) and then RIGHT(2), go back to LEFT buffer DmaRegs.CH2.DST_WRAP_SIZE = 0xFFFF; // Arbitary large value. We'll never hit this..... DmaRegs.CH2.SRC_WRAP_STEP = 2; // From starting address, move down 2 16-bit addresses to read next 32-bit word DmaRegs.CH2.CONTROL.bit.PERINTCLR = 1; DmaRegs.CH2.CONTROL.bit.SYNCCLR = 1; DmaRegs.CH2.CONTROL.bit.ERRCLR = 1; DmaRegs.CH2.MODE.bit.CHINTE = 1; // Enable DMA channel interrupts DmaRegs.CH2.MODE.bit.CHINTMODE = 0; // Interrupt at beginning of transfer DmaRegs.CH2.MODE.bit.PERINTSEL = 14; // McBSP MXEVTA DmaRegs.CH2.MODE.bit.CONTINUOUS = 1; // Enable continuous mode (continuously transmits) DmaRegs.CH2.MODE.bit.PERINTE = 1; // Enable interrupts from peripheral (to trigger DMA) } void I2CA_Init(void) { // Initialize I2C I2caRegs.I2CSAR = 0x001A; // Slave address - EEPROM control code #if (CPU_FRQ_150MHZ) // Default - For 150MHz SYSCLKOUT I2caRegs.I2CPSC.all = 14; // Prescaler - need 7-12 Mhz on module clk (150/15 = 10MHz) #endif #if (CPU_FRQ_100MHZ) // For 100 MHz SYSCLKOUT I2caRegs.I2CPSC.all = 9; // Prescaler - need 7-12 Mhz on module clk (100/10 = 10MHz) #endif I2caRegs.I2CCLKL = 100; // NOTE: must be non zero I2caRegs.I2CCLKH = 100; // NOTE: must be non zero I2caRegs.I2CIER.all = 0x24; // Enable SCD & ARDY interrupts // I2caRegs.I2CMDR.all = 0x0020; // Take I2C out of reset I2caRegs.I2CMDR.all = 0x0420; // Take I2C out of reset //zq // Stop I2C when suspended I2caRegs.I2CFFTX.all = 0x6000; // Enable FIFO mode and TXFIFO I2caRegs.I2CFFRX.all = 0x2040; // Enable RXFIFO, clear RXFFINT, return; } Uint16 AIC23Write(int Address,int Data) { if (I2caRegs.I2CMDR.bit.STP == 1) { return I2C_STP_NOT_READY_ERROR; } // Setup slave address I2caRegs.I2CSAR = 0x1A; // Check if bus busy if (I2caRegs.I2CSTR.bit.BB == 1) { return I2C_BUS_BUSY_ERROR; } // Setup number of bytes to send // MsgBuffer + Address I2caRegs.I2CCNT = 2; I2caRegs.I2CDXR = Address; I2caRegs.I2CDXR = Data; // Send start as master transmitter I2caRegs.I2CMDR.all = 0x6E20; return I2C_SUCCESS; } void Delay(int time) { int i,j,k=0; for(i=0;i for(j=0;j<1024;j++) k++; } void delay(Uint32 k) { while(k--); } //=========================================================================== // End of main() //=========================================================================== void init_mcbspa() { EALLOW; McbspaRegs.SPCR2.all=0x0000; // Reset FS generator, sample rate generator & transmitter McbspaRegs.SPCR1.all=0x0000; // Reset Receiver, Right justify word McbspaRegs.SPCR1.bit.RJUST = 2; // left-justify word in DRR and zero-fill LSBs McbspaRegs.MFFINT.all=0x0; // Disable all interrupts McbspaRegs.SPCR1.bit.RINTM = 0; // McBSP interrupt flag to DMA - RRDY McbspaRegs.SPCR2.bit.XINTM = 0; // McBSP interrupt flag to DMA - XRDY McbspaRegs.RCR2.all=0x0; // Clear Receive Control Registers McbspaRegs.RCR1.all=0x0; McbspaRegs.XCR2.all=0x0; // Clear Transmit Control Registers McbspaRegs.XCR1.all=0x0; McbspaRegs.RCR2.bit.RWDLEN2 = 5; // 32-BIT OPERATION McbspaRegs.RCR1.bit.RWDLEN1 = 5; McbspaRegs.XCR2.bit.XWDLEN2 = 5; McbspaRegs.XCR1.bit.XWDLEN1 = 5; McbspaRegs.RCR2.bit.RPHASE = 1; // Dual-phase frame McbspaRegs.RCR2.bit.RFRLEN2 = 0; // Recv frame length = 1 word in phase2 McbspaRegs.RCR1.bit.RFRLEN1 = 0; // Recv frame length = 1 word in phase1 McbspaRegs.XCR2.bit.XPHASE = 1; // Dual-phase frame McbspaRegs.XCR2.bit.XFRLEN2 = 0; // Xmit frame length = 1 word in phase2 McbspaRegs.XCR1.bit.XFRLEN1 = 0; // Xmit frame length = 1 word in phase1 McbspaRegs.RCR2.bit.RDATDLY = 1; // n = n-bit data delay, in DSP mode, X/RDATDLY=0 McbspaRegs.XCR2.bit.XDATDLY = 1; // DSP mode: If LRP (AIC23) = 0, X/RDATDLY=0, if LRP=1, X/RDATDLY=1 // I2S mode: R/XDATDLY = 1 always McbspaRegs.SRGR1.all=0x0001; // Frame Width = 1 CLKG period, CLKGDV must be 1 as slave // SRG clocked by LSPCLK - SRG clock MUST be at least 2x external data shift clk McbspaRegs.PCR.all=0x0000; // Frame sync generated externally, CLKX/CLKR driven McbspaRegs.PCR.bit.FSXM = 0; // FSX is always an i/p signal McbspaRegs.PCR.bit.FSRM = 0; // FSR is always an i/p signal McbspaRegs.PCR.bit.SCLKME = 0; #if I2S_SEL // In I2S mode: McbspaRegs.PCR.bit.FSRP = 1; // 1-FSRP is active low (L-channel first) McbspaRegs.PCR.bit.FSXP = 1 ; // 1-FSXP is active low (L-channel first) #else // In normal DSP McBSP mode: McbspaRegs.PCR.bit.FSRP = 0; // 0-FSRP is active high (data rx'd from rising edge) McbspaRegs.PCR.bit.FSXP = 0 ; // 0-FSXP is active high (data tx'd from rising edge) #endif McbspaRegs.PCR.bit.CLKRP = 1; // 1-Rcvd data sampled on rising edge of CLKR McbspaRegs.PCR.bit.CLKXP = 0; // 0- Tx data sampled on falling edge of CLKX McbspaRegs.SRGR2.bit.CLKSM = 1; // LSPCLK is clock source for SRG McbspaRegs.PCR.bit.CLKXM = 0; // 0-MCLKXA is an i/p driven by an external clock McbspaRegs.PCR.bit.CLKRM = 0; // MCLKRA is an i/p signal McbspaRegs.SPCR2.all |=0x00C0; // Frame sync & sample rate generators pulled out of reset delay_loop(); McbspaRegs.SPCR2.bit.XRST=1; // Enable Transmitter McbspaRegs.SPCR1.bit.RRST=1; // Enable Receiver EDIS; } 
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6个回答
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上图啊用干净的电源加滤波器
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可能是硬件上的信号干扰的问题，最好是上一下图吧
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现在看了一下信号图，ping和pong的输入信号就有问题，波形就不是单频波的波形，感觉可能是ping和pongDMA设置那里出了点问题吧。。。
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