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[问答] 请问芯片的稳定性会因使用的元件数量而异吗?
136 xilinx 芯片
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嗨,
我使用xilinx vivado -xc7a15tlcpg236-2L(Atrix 7系列)中的以下芯片进行设计的功率测量
(Vivado 2015.1)
我创建了一个频率为800Mhz的时钟并运行功率报告(在合成之后)。我试图模拟的设计是一个简单的piple线,它使用以下组件
资源
估计
可得到
利用率%
FF
76
20800
0.37
LUT
100
10400
0.96
I / O
36
106
33.96
BRAM
0.50
25
2.00
BUFG
1
32
3.13
当我合成一个小型缓冲器时,静态功率为0.067W,当我合成上述管道时,静态功率在0.067W时保持不变
我的问题是,芯片的稳定性是否会因使用的元件数量而异?
或者无论使用多少组件,它总是一个常数。
切换率和静态概率应该是多少?
应该是100%还是我应该使用默认选项(12.5和0.5)来估算管道的功率?
期待你的回复。
谢谢,
Vaibhav的

以上来自于谷歌翻译


以下为原文

Hi,

Im using the following chip in xilinx vivado - xc7a15tlcpg236-2L (Atrix 7 family)for power measurment of a design. (Vivado 2015.1)

I created a clock with a frequency of  800Mhz and ran the power report(after systhesis). The design which im trying to simulate is a simple piple line which uses the following components

Resource
Estimation
Available
Utilization %
FF
76
20800
0.37
LUT
100
10400
0.96
I/O
36
106
33.96
BRAM
0.50
25
2.00
BUFG
1
32
3.13



When i synthesize a small bufer, the static power is 0.067W and when i synthesize the above pipe line, the static power remais the same at 0.067W

My question is that whether the staic power of the chip would vary based on the number of components used? or will it be a constant always no matter how many ever components are used.

What should be the toggle rate and static probability? should both be 100% or should i use the default options (12.5 and 0.5) to estimate the power of pipe line?

looking forward to your reply.

Thanks,
vaibhav
0
2019-4-4 15:24:02   评论 分享淘帖 邀请回答
2个回答
五,
使用CLB时静态功率不会改变。
也不用于DSP。
对于使用或不使用的bram,它只会稍微改变一下。
在FPGA器件中,如果您使用或不使用,大多数都会通电。
动态功率随使用的频率,时钟频率和signaql的切换速率而变化。
常见的切换率不等,范围从12.5%到25%。
获得更高或更低的翻转率是罕见的。
一些设计,如加密器或解密器确实具有50%的切换率(下一个状态同样可能)。
DDR时钟是切换率的100%,但DDR数据可能只有25%到50%。
Austin Lesea主要工程师Xilinx San Jose

以上来自于谷歌翻译


以下为原文

v,
 
Static power will not change with CLB used, or not.  Nor for DSP used or not.  And it will change only very slightly for bram used or not.
 
In the FPGA device, most everything powered, if you use it or not.

Dynamic power varies with what is used, and how fast it is clocked, and the signaql's toggle rate.

Common toggle rate aberageds range from 12.5% to perhaps 25%.  It is rare to get higher, or lower toggle rates.  Some designs, like encryptors or decryptors do have a 50% toggle rate (the next state is equally probable).

DDR clock is 100% the toggle rate, but the DDR data is perhaps only 25% to 50%.
 
 
Austin Lesea
Principal Engineer
Xilinx San Jose
2019-4-4 15:29:21 评论

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---我的问题是芯片的静态功率是否会因使用的元件数量而异?
或者无论使用多少组件,它都将是一个常数。
静态功耗主要取决于静态供电电流。
静态电源电流不取决于所用组件的数量。
它取决于泄漏电流,这取决于器件中晶体管数量的数量。
Artix系列的静态电源电流值见表5(典型静态电源电流-page-4),网址为:xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf
- 切换率和静态概率应该是多少?
两者都应该是100%还是应该使用默认选项(12.5和0.5)来估算管道的功率?
切换速率会影响动态功耗(非静态功耗)。
切换率是网络或逻辑元件与其输入相比切换的速率。
切换率表示为百分比。
切换率反映了输出相对于给定输入或时钟输入的变化频率。
在具有上升或下降边缘同步元件的传统设计中,最大值可以是100%。
切换率为100%表示平均而言,输出在每个时钟周期内切换一次,使有效输出信号频率为时钟频率的一半。
如果同步元件使用两个时钟边沿,则最大值可以是200%。
切换率为200%表示输出在每个时钟周期内切换两次,改变时钟上升沿和下降沿,并使有效输出信号频率等于时钟频率。
在大多数情况下,该值的范围为12.5%至25%,因为同步元件上的输入不会在每个时钟边沿上切换。
仅供参考:以下答案记录对您有所帮助
http://www.xilinx.com/support/answers/63021.html
http://www.xilinx.com/support/answers/63020.html
http://www.xilinx.com/support/answers/63015.html
请参阅(UG907- http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug907-vivado-power-analysis-optimization.pdf)Power Analysis&
优化有关Tcl命令使用和信号速率或切换速率使用的更多信息。
另请参阅http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug440-xilinx-power-estimator.pdf
_______________________________________________如果有助于解决您的查询,请将此帖子标记为“接受为解决方案”。
因此,它将有助于其他论坛用户直接参考答案。如果您认为该信息有用且面向答复,请给予此帖子称赞。

以上来自于谷歌翻译


以下为原文

---My question is that whether the static power of the chip would vary based on the number of components used? Or will it be a constant always no matter how many ever components are used.
 
Static power majorly depends upon Quiescent Supply Currents. The Quiescent Supply Current does not depends upon on the number of components used. It depends upon leakage currents which is depends the number of transistors count in device. The Quiescent Supply Current values for   Artix family shown in Table 5 (Typical Quiescent Supply Current -page-4) in http://www.xilinx.com/support/documentation/data_sheets/ds181_Artix_7_Data_Sheet.pdf  
 
--What should be the toggle rate and static probability? Should both be 100% or should i use the default options (12.5 and 0.5) to estimate the power of pipe line?
 
Toggle rate affect the dynamic power consumption (Not static power). 
 
The toggle rate is the rate at which a net or logic element switches compared to its input(s). Toggle rate is expressed as a percentage. The toggle rate reflects how often an output changes relative to a given input or clock input. In a traditional design with rising or falling edged synchronous elements, the maximum value could be 100%. A toggle rate of 100% states that on average, the output toggles once during every clock cycle, making the effective output signal frequency half the clock frequency. If a synchronous element is using both clock edges, then the maximum value could be 200%. A toggle rate of 200% states that the output toggles twice during every clock cycle, changing on both rising and falling clock edges, and making the effective output signal frequency equal to the clock frequency. In the majority of cases, the value ranges from 12.5% to 25%, since the inputs on the synchronous elements do not toggle on every clock edge.
 
FYI: The below Answer records are helpful to you
http://www.xilinx.com/support/answers/63021.html
http://www.xilinx.com/support/answers/63020.html
http://www.xilinx.com/support/answers/63015.html
 
 Refer to (UG907- http://www.xilinx.com/support/documentation/sw_manuals/xilinx2015_1/ug907-vivado-power-analysis-optimization.pdf ) Power Analysis & Optimization for more information about Tcl command usage and signal rate or toggle rate usage.
 
Also refer http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_7/ug440-xilinx-power-estimator.pdf 
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2019-4-4 15:45:56 评论

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