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我们正在尝试构建运行Xilinx Embedded的Windows 7 64位/ Linux OS工作站,并且需要推荐的硬件表,特别是有关处理器规格的信息。
我们所有的工作站都将使用工作站classIntel Xeon芯片 - 更多核心但更昂贵的时钟速度与更便宜的消费级英特尔i7芯片一样高。 我们在哪里可以找到Xilinx嵌入式软件的推荐硬件文档? 我们无法找到这一点,需要协助选择高速处理器,并了解多核/多线程选项如何有利于或不会有利于整体压缩速度,例如使用如下所示的实施设计功能时。 以下是一些屏幕截图: 版本: 编译命令: 编译/实现期间的任务管理器: 我们尝试在Xilinx偏好位置启用多线程(2,4) - 任务管理器/处理器使用情况没有明显变化。 感谢您对此请求的任何帮助。 以上来自于谷歌翻译 以下为原文 We are trying to build Windows 7 64 bit / Linux OS workstations to run Xilinx Embedded and are in need of a recommended hardware sheet, especially regarding the processor specs. All of our workstations will use workstation class Intel Xeon chips – more cores but much more expensive to get clock speeds as high as the cheaper consumer class Intel i7 chips. Where can we find recommended hardware document for the Xilinx Embedded software? We cannot find this and need assistance choosing high speed processors and with understanding of how the multi core / multi thread options will benefit or not benefit the overall compiling speed such as when using the Implement Design function as shown below. Here are some screen shots: The version: The compile command: The Task Manager during compile / implement: We tried enabling Multi-threading (2, 4) in two Xilinx preference locations – no apparent change to the task managers / processor usage. Thank you for any assisatnce with this request. |
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可以找到ISE 14.3的发行说明。
ISE工具实际上是90年代粘合在一起的几个工具,它们已被用于每个新的FPGA架构。 不幸的是,这意味着这些工具采用90年代的软件技术设计,缺乏多种资源利用率。 它们主要是单进程和单线程,因此仅具有多个核心意味着其他可用核心将可用于系统上的其他任务。 多线程只会使任务在一个处理器核心的更多时间片上分裂。 使ISE工具运行得更快的唯一方法是减少CPU指令时间,增加内存缓存和/或总线速度,并减少HDD读/写时间(使用更大的FPGA有大量磁盘活动)。 Xilinx重写了他们的工具来解决这些问题,因为新系列FPGA的构建时间是不可接受的。 不幸的是,你需要使用7系列或UltraScale部件才能充分利用Vivado,所以如果你的目标是第6代或更老,那你就不走运了。 作为个人经验说明,我强烈建议不要在Map和PaR阶段使用多线程功能。 我过去曾与其他人讨论过这个问题(我相信使用的是ISE 12.x或13.x版本),并且人们一致认为多线程并没有产生与单线程相同的功能结果。 更常见的是,结果似乎根本不起作用。 -约旦 这个签名故意留空。 以上来自于谷歌翻译 以下为原文 Release notes for ISE 14.3 can be found here. The ISE tool is really several tools that were glued together in the 90's and they've been re-hashed for each new FPGA architecture. Unfortunately, that means the tools were designed with 90's software techniques and a lack multi-resource utilization. They're primarily single process and single thread, so having multiple cores only means the other free cores will be available to other tasks on your system. Multithreading only makes the task get split across more time slices of one processor core. The only ways to get the ISE tools to run faster are deceasing CPU instruction time, increasing memory cache and/or bus speeds, and reducing HDD read/write times (there's lots of disk activity with larger FPGAs). Xilinx rewrote their tools to fix these problems as build times for the newer families of FPGAs were unacceptable. Unfortunately, you need to be using 7 series or UltraScale parts to take advantage of Vivado, so if you're targeting something 6th generation or older, you're out of luck. As a personal experience note, I strongly recommend not using the multithreading capability in the Map and PaR stages. I have discussed this with others in the past (I believe using ISE 12.x or 13.x releases) and there was a consensus that the multithreading did not produce the same functional results as the single threaded. More often, it seemed the results were not functional at all. -Jordan This signature intentionally left blank. |
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