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嗨,
我正在尝试在Cadence上设计ADC模拟,但我的教授说我可以模拟Cadence上的模拟部分,然后在批处理文件中输出模拟值。 使用批处理文件中的值作为FPGA(Xilinx Virtex-6)的输入,FPGA具有ADC的其余数字电路,我可以使其工作。 这可能吗? 任何人都可以提供链接到我可以阅读更多内容的来源吗? 任何帮助,将不胜感激。 谢谢! 以上来自于谷歌翻译 以下为原文 Hi, I am trying to design an ADC simulation on Cadence but my professor says that I can simulate the analog portion on Cadence and then output the simulation values in a batch file. Using the values in the batch file as inputs to the FPGA (Xilinx Virtex-6), which has the rest of the digital circuit of the ADC, I can make it work. Is this possible? Can anyone provide me links to sources where I can read more on this? Any help would be appreciated. Thanks! |
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aliasnikhil写道:
嗨, 我正在尝试在Cadence上设计ADC模拟,但我的教授说我可以模拟Cadence上的模拟部分,然后在批处理文件中输出模拟值。 使用批处理文件中的值作为FPGA(Xilinx Virtex-6)的输入,FPGA具有ADC的其余数字电路,我可以使其工作。 这可能吗? 任何人都可以提供链接到我可以阅读更多内容的来源吗? 任何帮助,将不胜感激。 谢谢! 编写ADC的总线功能模型很容易,并使用real类型作为输入“电压”。 Cadence的仿真工具版本也支持VHDL-AMS,它增加了混合信号仿真支持。 我的猜测是你使用Cadence工具作为教育许可证的一部分,而你的教授很可能是支持联系人,所以请与他交谈。 ----------------------------是的,我这样做是为了谋生。 以上来自于谷歌翻译 以下为原文 aliasnikhil wrote:It's easy enough to write a bus-functional model of an ADC, and use type real as the input "voltage." Versions of Cadence's simulation tools also support VHDL-AMS, which adds mixed-signal simulation support. My guess is that you use the Cadence tools as part of an educational license, and your professor is likely the support contact, so talk to him. ----------------------------Yes, I do this for a living. |
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谢谢Eilert!
我想要做的是在Cadence上设计一个VCO(ADC的模拟部分)。 然后模拟它并使用Cadence将VCO输出存储在文件中。 然后我将使用该文件将VCO的输出提供给我的ADC的数字部分,这些部分位于Virtex-6上,并将FPGA本身的输出作为模数转换器的数字输出。 从数字部分到模拟部分没有反馈路径。 显然这将是一个问题。 幸运的是,它不是必需的。 可以这样做吗? 对不起,我上次没那么描述。 但是,从我教授的说法来看,这是一个非常标准的做法,我可能会问一个愚蠢的问题。 谢谢! 以上来自于谷歌翻译 以下为原文 Thanks Eilert! What I am trying to do is design a VCO (analog portion of the ADC) on Cadence. Then simulate it and store the VCO output on a file using Cadence. Then I will use this file to provide the outputs of VCO to the digital portion of my ADC, which are on Virtex-6, and get the outputs from the FPGA itself as the digital out of my Analog-to-Digital converter. There is no feedback path from the digital portion to the analog portion. Obviously it will be a problem. Fortunately, it is not required. Can this be done? Sorry I wasn't so descriptive last time. I though, judging from the way my professor said it, that it is a very standard practice to do this and I am probably asking a silly question. Thanks! |
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嗨,
因此,对于VCO,您正在进行电压到频率转换,而FPGA只是用作频率测量单元,可以生成与VF转换相关的输出,以查看输入电压的值。 但是(简单的)频率测量单元可以自行验证。 至少对于功能验证。 当您要检查组合ADC电路的动态行为和线性属性时,组合方法可能会很有用。 但是,你必须至少在模拟仿真器中放置FPGA输入电路(如何获得模型?),以查看数字输入对VCO输出产生的信号的真实响应。 不要忘记模拟PCB属性! 那么你想通过结合模拟找到什么呢? VCO的行为也可以在VHDL测试平台中轻松实现。 vco_out = not vco_out after(vco_base_period /(2 * Uin)); - 一个非常简单的VCO模型; 不要使用Uin = 0 如果您的教授认为这是一种标准方法,他可能会为您提供在您所在机构完成的前项目的示例。 ;-) 你还没有提到你将要使用的模拟器。 例如,Bassman提到在节奏工具中有一些VHDL-AMS模拟器。 有了这个,你可以在一个工具中进行模拟,而不需要进行文件传输。 也许您可能需要将Xilinx库编译到该模拟器并手动进行模拟,而不是从ISE IDE进行模拟。 但是,当您已经使用Cadence工具时,这应该没问题。 有一个很好的模拟 Eilert 以上来自于谷歌翻译 以下为原文 Hi, so, with the VCO you are doing a Voltage to frequency conversion and the FPGA just acts as a frequency measuring unit that generates an output with respect to the VF-conversion to see the value of the input voltage. But a (simple) frequency measurement unit can be verified all for it self. At least for the functional verification. The combined approach might become useful when you are about to check for dynamic behavior and linearity properties of the combined ADC circuit. But then you have to put at least the FPGA input circuit in the analog simulator too (How to get the model?) to see the true response of the digital input to the signal generated by the VCO output. And don't forget to model the PCB properties! So what actually do you want to find out by combining the simulations? the behavior of a VCO can easily be modeld in a VHDL testbenchg as well. vco_out = not vco_out after (vco_base_period /(2*Uin)); -- a very simple VCO model; don't use Uin=0 If your proffessor sais this to be a standard method he probably can provide you with examples of former projects done at your institution. ;-) Still you didn't mention which simulators you are about to use. Bassman mentioned for example that there is some VHDL-AMS Simulator among the cadence tools. Withthat one you could do the simulation within one tool, and wouldn't need to do the file transfer thing. maybe you might need to compile the Xilinx libraries to that simulator and do the simulation manually rather than from the ISE IDE. but that should be no problem when you are already working with Cadence tools. Have a nice simulation Eilert |
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