完善资料让更多小伙伴认识你,还能领取20积分哦, 立即完善>
我需要以同步方式驱动PSoC5 LP输出引脚。我正在考虑将比特编码[Byth]放入内存区域,然后使用DMA将该内存,一个8位字节或16位字一次传送到[Roal/UDB}组件中。这个想法是,DMA和组件将一起工作,这样我就永远不会有传输下溢,所以我的同步输出引脚永远不会有“故障”。这与处理器的高强度使用保持了相同。
所以,我不会马上找到一个很好的例子源代码。这不是RS232或SPI或音频。我的想法是使用一个“移位寄存器”组件。然后我需要把DMA组件绑在移位寄存器上。然而,如果所有必要的控制特性都在那里,我也不知道。这个想法是,DMA会在移位寄存器*中填充一个保持寄存器,在移位寄存器是空的之前,使它在没有下溢的情况下及时加载。因此,在我看来,DMA组件NRQ输出需要驱动移位寄存器负载输入。但是,DMA组件需要知道何时该做下一步,所以移位寄存器中断输出可能会驱动DMA DRQ输入。我只是不确定这些行为是否正常。 也许我的问题是这个。我是用正确的方法,用移位寄存器吗?还是有更好的方法呢? 同样,重复,我需要这个引脚输出一个时间控制,又名同步,输出。我想用内存阵列中的位来控制它。(注意这个引脚是自定时的。没有单独的时钟。 谢谢, 赫尔穆特 以上来自于百度翻译 以下为原文 I have a need to drive a PSoC 5 LP output pin in a synchronous manner. I'm thinking of putting bit-coded [bytes] into a memory area, and then using DMA to transfer that memory, one 8-bit byte or 16-bit word at a time, into a [hardware/UDB} component. The idea is that the DMA and component will work together so that I never have a transmit underflow, and so my synchronous output pin never has a "fault". This is in contrast to high-intensity use of the processor to keep the thing fed. So, I don't immediately find a good example source code. This isn't RS232 or SPI or audio. My thought is to use a "Shift Register" component. Then I would need to tie the DMA component to the shift register. I don't know, however, if all the necessary control features are there. The idea is that the DMA would fill a holding register in the Shift Register *before* the shifting register is empty, so that it gets side loaded in time, without underflow. So it seems to me that the DMA component nrq output needs to drive the Shift Register Load input. But then, the DMA component needs to know when it's time to do the next, so maybe the Shift Register interrupt ouput drives the DMA drq input. I'm simply not sure if these things behave properly. Perhaps my question is this. Am I going about this the correct way, trying to use the Shift Register? Or is there a better way. Again, to repeat, I need this pin to output a time-controlled, aka synchronous, output. I want to control it using bits in a memory array. (Note this pin is self-timed. There is no separate clock.) Thanks, Helmut |
|
相关推荐
4个回答
|
|
赫尔穆特,有移位寄存器,你可以连接到一个端口,并使用第一次测试“穷人的DMA”(CPU)来填充它们。在以后的阶段,你可以使用真正的DMA。
鲍勃 我位于不来梅附近。 以上来自于百度翻译 以下为原文 Helmut, there are shift registers which you can connect to a port and fill them using at first test "poor man's DMA" (CPU). At a later stage you could use real DMA. Bob PS: I am located near Bremen |
|
|
|
我发明了HTTP://www. CyPr.com/FoMU/PSOC-5 DEVICE编程/DMA-SHIVET-RealStase-这是接近的,但在我看来,我已经极大地简化和改进了它。该引用不能背靠背输出字节。我的修改可以,而且更简单。
我已经将PWM降低到单个固定函数PWM,使用移位寄存器负载信号的逆,以便将DMA触发到移位寄存器FIFO中。一个明显的副作用是DMA定时。原来的设计DMA WIFT的FIFO可能是一个单一的主时钟之前,它已加载到移位寄存器。我的设计DMA在负载之后写下一个FIFO值一个移位时钟。这将我的数据输出延迟了一个字节。但是,它允许PWM仅计数为8,而不是最初设计的9或22的最小值。以这种方式,字节以真正同步方式背靠背移位。 下面是一个范围捕获(嘿,我负担不起一个新的范围)显示负载和数据引脚。 我已经附上完整的项目。 请注意,我自己的需求必须传输一个突发,而不是无限循环。我几乎都在工作,希望尽快公布结果。它涉及从DMAYNRQ中加入一些反馈逻辑到PWM和SHIVTREGY1的复位输入。 -赫尔穆特 不来梅?哦,好吧。离斯图加特或美国/欧洲/印度国际机场太远。也许下次吧… 移位寄存器DMA背靠背 2.6兆字节 以上来自于百度翻译 以下为原文 I found http://www.cypress.com/forum/psoc-5-device-programming/dma-shift-register which is close, but I have dramatically simplified and improved it in my opinion. That reference can NOT output bytes back-to-back. My modification CAN, and is more simple. I have reduced the PWM to a single fixed function PWM, using the inverse of the shift register LOAD signal in order to trigger DMA into the shift register FIFO. One distinct side effect is that the DMA timing. The original design DMA-wrote the FIFO perhaps a single master clock before it got loaded into the shift register. My design DMA-writes the NEXT FIFO value one shift clock AFTER the LOAD. This delays my data output by one byte. But, it allows the PWM to only count to 8, rather than a minimum of 9 or even 22 as originally designed. In this way, the bytes are shifted out back-to-back in a true synchronous fashion. Below is a scope capture (hey, I can't afford a new scope) showing LOAD and DATA pins. I have attached the complete project. Note that my own need must transmit a single burst, rather than looping indefinitely. I have that almost working and hope to post the result soon. It involves adding some feedback logic from DMA_NRQ to the reset input of the PWM and ShiftReg_1. -Helmut P.S. Bremen? Oh well. Too far from Stuttgart or a US/Europe/India international airport. Maybe next time... |
|
|
|
我相信我有多个背对背同步字节的单个突发工作。我已经添加了5个从“离散”逻辑构建的S—R触发器,在从DMAYNRQ到PWMY1和SHIVETREG1的复位输入的反馈回路中。TrutGryReg设置所有它们,导致NututPuthAc能能能行(AKA重置)变低。这一切都开始了。后来,当DMAYNRQ脉冲仅高达2个主时钟时,它重置了FiFSTFF。但是,由于延迟的数据,还有一个字节尚未发送。当最后一个字节的负载上升时,下一个FF就会复位。当负载再次变低时,下一个FF就会复位。下一个FF重置当负载高,但再一次。现在已经接近最后一个字节完成传输,而下一个不存在的字节将被加载。注意还有一个延迟,当负载再次变低时,下一个FF被重置。(数据在加载后一段时间出来。我相信这是因为它在看到负载后才移动。这是乳清,最后一个额外的FF是必需的。)
请注意,软件集然后在开始时清除TrutGryReg以启动事务。因此,TurgGeReg在突发期间一般为0。 注意,我假设所有这些“非但”和“门”不会消耗太多的资源。如果他们这样做,那么… 一个更简单的替代方案是将DMAYNRQ馈入中断。TrutGryReg直接进入复位输入,因此软件将其设置为低,以启动断开并使其保持低电平。中断例程设置TrutGryReg停止进一步传输。组件名称逻辑现在被反转。也许添加一个反相器来让这个名字更有意义。)这样做的副作用是DMA突发中的最后一个字节不会被传输,所以你需要提供一个虚拟尾随字节。此外,下一个最后字节只会部分传输,所以它也需要是一个虚拟的,并且只传输它的一部分的情况需要是可接受的。BIDTEXX00两个虚拟机都应该有帮助。 下面是顶部设计,范围照片和附加项目。作用域SurnSututPutsApple在爆裂期间活动为低,然后是数据。我做了最后一个BYTEX0A5,这样我就可以看到第一个和最后一个位,以确保他们都出来了,他们做到了。 我的特定应用程序将使用UnEndoPutsAc能能能行键对一个收音机(PTT =推到通话),然后发送数据作为FSK。 -赫尔穆特 移位寄存器DMA单突发背对背Bythy1.Zip 2.8兆字节 以上来自于百度翻译 以下为原文 I believe I have the single burst of multiple back-to-back synchronous bytes working. I've added 5 S-R Flip Flops built from "discrete" logic, in a feedback loop from DMA_NRQ to the reset input of the PWM_1 and ShiftReg_1. Trigger_Reg sets all of them, causing nOUTPUT_ACTIVE (aka reset) to go low. This starts everything. Later, when DMA_NRQ pulses high for only 2 master clocks, it resets the frist FF. However, due to the delayed data, there is still another byte that hasn't been sent yet. The next FF gets reset when LOAD rises for that last byte. The next FF gets reset when LOAD goes low again. The next FF gets reset when LOAD goes high yet one more time. This is now close to when that last byte is finished transmitting and the next non-existent byte is to get loaded. Note there's one more delay, for the next FF getting reset when LOAD once again goes low. (The data is coming out one bit time after LOAD. I believe that's because it doesn't shift until the clock after seeing LOAD. That's whey the very last extra FF is required.) Note that the software sets then clears Trigger_Reg in the beginning to start things off. Thus, Trigger_Reg is general 0 during the burst. Note I'm assuming all these NOR and AND gates don't eat up too much resource. If they do, then... A more simple alternative to this would be to feed the DMA_NRQ into an interrupt. Trigger_Reg goes DIRECTLY to the reset inputs, so the software sets it low to start things off and leaves it low. The interrupt routine sets Trigger_Reg to stop further transmission. (The component name logic is now inverted. Perhaps add an inverter to make the name make better sense.) A side effect of this is that the last byte in the DMA burst won't get transmitted, so you need to provide a dummy trailing byte. Furthermore, the next-to-last byte will only be partially transmitted, so it needs to be a dummy as well, and the situation of transmitting only part of it needs to be acceptable. Making both dummy bytes 0x00 should help. Below are the top design, a scope photo, and attached project. The scope shows nOUTPUT_ACTIVE going low during the burst, and then the DATA. I made the last byte 0xA5 so that I could see the first and last bits to make sure they all came out OK, which they do. My specific application will use nOUTPUT_ACTIVE to key a radio (PTT = Push-To-Talk) and then send the DATA out as FSK. -Helmut |
|
|
|
“我假设所有这些与非门不会消耗太多的资源。如果他们这样做,那么……“在创造者窗口的右边是资源表标签。这可能有助于你估计免费资源。
鲍勃 以上来自于百度翻译 以下为原文 "I'm assuming all these NOR and AND gates don't eat up too much resource. If they do, then..." On the very right hand side of the Creator window is a resource meter tab. This might help you estimating free resources. Bob |
|
|
|
只有小组成员才能发言,加入小组>>
715个成员聚集在这个小组
加入小组1896 浏览 1 评论
1651 浏览 1 评论
3401 浏览 1 评论
请问可以直接使用来自FX2LP固件的端点向主机FIFO写入数据吗?
1567 浏览 6 评论
1379 浏览 1 评论
CX3连接Camera修改分辨率之后,播放器无法播出camera的画面怎么解决?
180浏览 2评论
179浏览 2评论
使用stm32+cyw43438 wifi驱动whd,WHD驱动固件加载失败的原因?
318浏览 2评论
344浏览 1评论
58浏览 1评论
小黑屋| 手机版| Archiver| 电子发烧友 ( 湘ICP备2023018690号 )
GMT+8, 2024-4-20 12:20 , Processed in 0.738037 second(s), Total 73, Slave 62 queries .
Powered by 电子发烧友网
© 2015 bbs.elecfans.com
关注我们的微信
下载发烧友APP
电子发烧友观察
版权所有 © 湖南华秋数字科技有限公司
电子发烧友 (电路图) 湘公网安备 43011202000918 号 电信与信息服务业务经营许可证:合字B2-20210191 工商网监 湘ICP备2023018690号