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[问答] 可以对两个标准复合视频信号进行时分复用
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嗨,大家好,
我是FPGA电子设计的新手。
去年我做了一个VHDL主题,我留下了一个Spartan-3 Digilent主板。
我对一个项目有一个讽刺的想法。
这对我的水平来说可能太多了,但无论如何我还是想问。
我可以对两个标准复合视频信号进行时分复用,以便使用两个ADC将其复用为一个吗?
在斯巴达3板上可行吗?
TDM是否足够或只能由FDM完成?
有什么考虑?
这有多难?
如果是,并且由于我只有一块电路板,我可以将多路复用信号返回到同一电路板,将其解复用并通过两个DAC吗?
非常感谢,如果我的问题有点愚蠢,我很抱歉。

以上来自于谷歌翻译


以下为原文

Hi everyone,
I'm new to FPGAs and electronic design. I did a VHDL subject last year and I was left with a Spartan-3 Digilent board.

I had a crasy idea about a project. It probably too much for my level but I thought to ask anyway.

Can I peRForm time division multiplexing on two standard composite video signals in order to multiplex it in to one using two ADCs?

Is that doable on the spartan-3 board?

Will TDM be enough or can be only done by FDM? What are the considerations? How dIFficult this will be?

If yes and since I only have one board, can I return the multiplexed signal into the same board, demultiplex it and pass it through two DACs?

Thank you very much and sorry if my questions were a bit silly.
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2019-1-16 09:20:12   评论 分享淘帖 邀请回答
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嗨,乔治,
你的想法似乎并非不可能。
一如既往,它需要适当的计算和设计。
你打算用什么ADC?
这将为您提供采样率和数据宽度。
将它乘以2,您就拥有了传输接口所需的数据速率(无论它是什么)。
由于Spartan 3 FPGA能够处理超过100MHz的(实际平均)系统时钟,因此速度应该没有问题。
面积也应该没问题。
两个通道的TDM不会消耗太多逻辑。
棘手的部分可能会处理视频,tdm传输和同步数据的不同时钟域。
就像脑筋急转弯一样,尝试计算出基本的设计参数,并对FPGA设计(接口和数据处理模块)进行概述。
一旦你计算出一些实数,你会发现问题变得更加清晰和简单。
有一个很好的综合 
Eilert

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Hi George,
your idea doesn't seem to be impossible.
As always it needs proper calculations and design.
 
What ADCs are you intending to use?
This will give you the sample rate and data width.
Multiply it by two and you have the data rate required for your transmission interface (whatever it will be).
 
Since Spartan 3 FPGAs are capable of working with (realistic average) system clocks of over 100MHz there should be no problem with speed.
Area should also be no problem. TDM of two channels doesn't consume too much logic.
 
The tricky parts will probably be handling the different clock domains for video, tdm-transmission and synchronizing the data.
 
Just as a brain teaser, try to work out the basic design parameters and make a outline for the FPGA design (interfaces and data handling modules).
You will see that the problem becomes clearer and simpler once you worked out some real numbers.
 
Have a nice synthesis
  Eilert 
 
 
 
2019-1-16 09:25:53 评论

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您好,谢谢您的回复。
关于转换器,我发现ADV7127(三重DAC,10位,0.5到240 MHz)采用更友好的TSSOP24封装。
所以我想结合2个甚至3个10位源,每个让1MHz。
对于3个通道,我的速率为10Mbit / sec,1为20,2为30Mbits / sec。
这是一个现实的价值吗?
我要降低时钟吗?
你能告诉我一个时钟值吗?
谢谢。

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Hello and thank you for your reply.
 
Regarding the converters I found the ADV7127 (triple DAC, 10-bits, 0.5 to 240 MHz) that comes in a more friendly package TSSOP24.
 
So I want to combine 2 or even 3 10-bit sources in lets say  1MHz each. I will have a bitrate of 10Mbit/sec for 1, 20 for 2 and 30Mbits/sec for 3 channels.
 
Is that a realistic value? Shall I lower down the clock? Can you suggest me a clock value.
 
Thank you.
2019-1-16 09:31:59 评论

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对不起,我刚刚意识到ADV7123是单个DAD所以我必须选择ADV7123。

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Sorry, I have just realised that the ADV7123 is a signle DAC so I will have to go for a the ADV7123.
2019-1-16 09:50:00 评论

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嗨,乔治,
再想一想您的视频源和Datarate。
你说那里你想使用复合视频信号。
一行具有52μs的视频数据,总长度为64μs。
因此,对于1MHz,您只能在该行中生成52个像素。
看电视真的没什么用,不是吗?
那么,让我们向后计算:
你想要的屏幕分辨率是多少?
640 x 480?
我们假设这个。
所以你有640 x 480像素* 50(非交错)帧每秒=分钟。
15360000 Hz Pixelclock。
真正的Pixelclock会更高一些,因为你没有可用于像素的全部时间。
您还需要时间进行同步。
(你也可以每秒使用60帧)
所以我们谈论的是每个通道的16MHz数据速率,多次使用三个将为我们提供48MHz的多路复用数据。
这可以在简单的FPGA中轻松处理。
但我们仍然保持数据并行。
我认为视频8位RGB就足够了(只需将DAC的两个LSB钳位到地),因此我们有24个数据线。
48MHz * 24Bit eqals 1.152Gbps。
除非您不打算在Virtex设备中使用某些千兆位收发器,否则这太过分了。
但是让我们来看看像DVI等数字视频接口,他们使用多行来降低数据速率。
让我们保持简单并将R,G和B的每个位复用在一行中,因此我们有8个Datalines。
这些可以通过LVDS以约150Mbps的速率传输(或内部传输,用于测试目的)。
所以它仍然可能取决于您项目的实际需求。
这不是新手的设计,但你会随着项目而成长。
顺便说一句。
也许现在你明白了,为什么你选择的视频DAC高达240 MHz。
如果没有,请尝试计算平均计算机显示器或HDTV分辨率的像素时钟。
:-)
有一个很好的综合 
Eilert

以上来自于谷歌翻译


以下为原文

Hi George,
Think again about your video sources and the Datarate.
You said there that you want to use  composite video signals.
One line has 52µs video data and an overall length of 64µs.
So, with 1MHz you can only generate 52 pixels in that line.
Not really useful for watching TV, isn't it?
 
So, let's calculate backwards:
What's your desired screen resolution?  640 x 480?
let's just assume this. So you have  640 x 480 Pixels * 50 (noninterleaving) Frames per second =   min. 15360000 Hz Pixelclock.
The true Pixelclock will be somewhat higher, because you have not the whole time available for your pixels. You also need time for synchronisation.
 (Also you might use 60 Frames per second)
 
 
So we are talking of about 16MHz  datarate per channel multyplied by three will give us 48MHzfor the multiplexed data.
That can be handled quite easily in a simple FPGA. 
But we still have the Data in parallel. I think for video 8-bit RGB is sufficient (just clamp the two LSBs of your DAC to ground) so we have 24 datalines.
48MHz * 24Bit eqals 1.152Gbps. Unless you are not about to use some Gigabit Transcevers in a Virtex device this is just too much.
But let's take a look at Digital Video Interfaces like DVI etc., they are using multiple lines to reduce the datarate.
Let's keep it simple and multiplex each bit of R,G&B in a single line, so we have 8 Datalines.
These can be transmitted with about 150Mbps over LVDS (or internally, for testing purposes).
So it's all still possible depending on the real needs for your project.
It's not really a design for newbies, but you will grow with the project.
 
btw. Maybe now you get an idea , why the video DAC you chose goes up to 240 MHz.
If not, try to calculate the pixel clock for an average computer display or HDTV-resolution. :-)
 
Have a nice synthesis
  Eilert 
 
 
 
 
2019-1-16 10:07:45 评论

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你是对的,这不是新手的设计。
我完全错了。
我想的是ADC的10位输出是一大块视频(可能是一帧),我可以在一个20位字上组合两个10位输出并发送它。
据我所知,它有点复杂。
我订购了一本关于视频工程的书,其中包括DtoA和atoD视频转换,如果我没记错,还包括视频传输。
希望我能够更多地了解它。
感谢您的评论,但一切看起来仍然让我感到困惑。
我找到了一个ADC,即AD9203。
那么ADC的10位输出是什么?
是视频线还是像素?
你提到R G和B,我想输入和输出复合,我还需要用RGB处理数字化视频吗?
非常感谢你。

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You were right, it is not design for newbies.
I had completely the wrong idea. What I thought is that the 10-bit output of the ADC is a large chunk of video (a frame perhaps) and that I can combine two 10-bit outputs on a single 20-bit word and send it. from what I understand it is a bit more complicated.
 
I ordered a book on Video-Engineering that includes DtoA and atoD video conversion and if I remember correctly includes video transmission. Hopefully I will be able to understand it a bit more.
 
Thank you for your comments but everything still looks a bit confusing to me.
 
I found an ADC, the AD9203. So what is a 10-bit output from a ADC? Is it a video line or a pixel?
 
You mentioned R G and B, I thought to input and output composite, Do I still need to process the digitised video by RGB?
 
Thank you very much.
 
 
2019-1-16 10:26:11 评论

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嗨,乔治,
我假设你会使用一个特殊的ADC将复合信号分解成RGB元素。
您的方法更直接,但也会以类似的方式工作。
这里唯一要考虑的是图片质量。
复合信号有点棘手,因为它是(好的......)由亮度信号和调制的彩色信号(色度)组成。
因此,当您要对复合视频信号进行数字化时,10个采样将导致质量差(带宽为5.57MHz,因此不满足Fs> 2B),
实际值范围在20-25 MSPS区域(越多越好),并且应使用ADC的完整10位分辨率。
你看,数据速率之间的差异将是最小的。
我们现在的数据位较少,但采样频率较高。
来自ADC的样本将适用于像素,仍然不是每个样本都是像素(例如,在同步时间期间),并且我们需要对调制的颜色信号进行一些过采样。
因此,这是一个简单的计算,对于像素的重建,必须组合3-4个样本以再现正确的颜色值。
这是一个关于视频信号采样和生成等(德国)学生项目工作的链接:
http://www.informatik.uni-hamburg.de/bib/medoc/Doc-032.pdf
如果你不能阅读文字,也许图片和公式对你的目的有点帮助,或者你可能会找到类似的英语作品。
有一个很好的综合 
Eilert

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以下为原文

Hi George,
I assumed that you would use a special ADC that decomposes the composite signal into it's RGB-elements.
Your approach is more straightforward, but will work in a similar way. The only thing to consider here ispicture quality.
The composite signal is a little tricky because it's, (well...) composed from the luminance signal and a modulated color signal (chrominance).
So, when you are going to digitize a composite video signal 10 megasamples would result in a poor quality (the bandwith is 5.57MHz so Fs >2B is not satisfied),
Practical values are ranging in the 20-25 MSPS area (The more the better) and the full 10 bit resolution of your ADC should be used.
You see, the difference between the data rates will be minimal. We have less data bits now, but a higher sampling frequency.
 
A sample from your ADC will be adeqate to a pixel, still not every sample is a pixel (e.g. during sync time) and we need some oversampling for the modulated colour signal.
So it's a simple calculation that for the reconstruction of a pixel 3-4 samples have to be combined to reproduce the correct colour value.
 
 Here's a link to a (german) students project work about video signal sampling and generation etc.:
 http://www.informatik.uni-hamburg.de/bib/medoc/Doc-032.pdf
 If you cant read the text, maybe the pictures and formulas a re somewhat helpful for your purpose, or you may find a similar english work.
 
 Have a nice synthesis
  Eilert
 
 
 
 
2019-1-16 10:39:21 评论

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你好,
我花了一些时间来完成这个项目,但现在我想再开始考虑一下。
我想使用将连接到Spartan-3评估板的tripple DAC ADV7123制作PCB。
之后我想用三个AD9203 ADC制作另一个PCB,并将它连接到S3评估板。
最初我只是将三个独立的复合视频源转换为数字视频,将它们传递到S3板,将它们直接取出并再次转换为模拟。
当我这样做时,我将开始考虑多路复用算法。
那可行吗?
我的想法有什么缺陷吗?
请回答我那些我还不了解的事情。
非常感谢你。

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Hello,
 
I took some time out of this project but now I would like to start thinking about it again. I would like to make a PCB using the tripple DAC ADV7123 that will be connected to the Spartan-3 evaluation board.
 
After that I would like to make another PCB with three  AD9203 ADCs and connect it as well to the S3 eval board.
 
Initially I will just convert three separate composite video sources into digital, pass them through the S3 board, take them out direclty and convert them to analog again. When I do that, I will start thinking about the multiplexing algorithm.
 
Is that doable? Are there any flaws on my idea. Please answer me as there things that I dont understand yet.
 
Thank you very much.
 
 
2019-1-16 10:50:13 评论

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嗨,乔治,
ADV7123似乎是一个不错的选择,并且所有内容都是并行运行的,因此一个或三个通道不应成为问题。
当然,您可能需要检查是否有足够的阻塞可以作为三个输入和输出的行缓冲器(以及其他您将要在FPGA中实现的功能)。
因此,如果您可以将转换器连接到您的电路板,我认为没有理由说它不应该工作。
有一个很好的综合 
Eilert

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Hi George,
the ADV7123 seems a good choice, and everything runs in parallel, so one or three channels shouldn't be an issue.
Of course you may have to check wether you have enough blockrams that can serve as line buffers for three inputs and outputs (and otherstuff you are going to implement in the FPGA).
 
So, if you can attach the converters to your board, I see no reason why it shouldn't work.
 
Have a nice synthesis
  Eilert
2019-1-16 11:00:45 评论

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嗨,谢谢你的回复,
在我要制作的ADV7123 PCB上,我需要22欧姆的直插式电阻和4.7kΩ的拉式电阻来控制DAC的数字和控制输入吗?
这将增加60多个电阻。
我可以摆脱它们吗?
我需要DAC输入端的缓冲器吗?
我想在外部使用专用缓冲区,但是你提到如果我理解正确的话,我可以在FPGA内部实现缓冲区。
您之前说过,DAC的时钟的实际值应该是25MHz。
我可以使用S3 eval PCB的onbord时钟来生成DAC采样吗?
或者我应该适合一个外部的?
非常感谢你

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Hi and thank you for your reply,
 
On the ADV7123 PCB that I'm going to make, do I need 22ohms in-line resistors and 4.7kohms pull-upp resistors on the digital and controls inpuits of the DAC? This will add more than 60 resistors. Can I get rid of them?
 
Do I need buffers on the inputs of the DAC? I was thinking of using dedicated buffers externally but you mentioned that I can implemet the buffers inside the FPGA if  I understand correctly.
 
You said before that a realistic value for the clock for the DAC should be at 25MHz. Can I use the onbord clock of the S3 eval PCB to generate the DAC sampling? or shall I fit an externall one?
 
Thank you very much
 
 
2019-1-16 11:07:20 评论

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嗨,乔治,
这么多问题,让我们看看......
我不知道你为什么要连接这么多电阻器。
只是为了安全还是需要进行关卡翻译?
同样的问题是针对缓冲区(如74xx540 / 541)。
如果DAC I / O电压与FPGA兼容,则不需要其中任何一个。
对于I / O级转换,芯片可能工作得更好。
如果你真的需要电阻器,那么你可以用4到10个电阻器的阵列购买它们,这样你最终会得到少量具有多个电阻器的类似芯片的器件。
我认为S3e板带有50MHz时钟源,因此使用其中一个FPGA DCM,您可以轻松创建所需的频率。
也许,无论如何,当你从DAC开始时,你可以从FBAS时序的简单设计开始,只是视频内容的一些计数器值。
因此,您可以获得一个简单的视频模式生成器来测试您的fbas输出,甚至可以在您连接ADC的最终设计中重复使用FBAS Timing生成器。
有一个很好的综合 
Eilert

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以下为原文

Hi George,
so many questions, well let's see...
I don't know why you want to attach so many resistors. just for safety or are they needed for level translation? 
Same question is for the Buffers (like 74xx540/541).
 
If the DAC I/O voltages are compatible with the FPGA you don't need either of them. For I/O level translation the chips probably work better.
If you really need the resistors, then you can buy them in arrays of 4 to 10 resistors, so you end up with a small number of chiplike devices with multiple resistors.
 
I think the S3e board comes with a 50MHz Clock source, so with one of the FPGAs DCMs you can easily create the frequency you need.
 
Maybe, while you start with the DAC anyway, you can begin with a simple design for the FBAS timing and just some counter values for the video content.
So you get a simple video pattern generator to test your fbas output, and even can reuse the FBAS Timing generator in your final design where you attach the ADCs.
 
Have a nice synthesis
  Eilert 
 
2019-1-16 11:17:49 评论

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