gaped到un-gaped时钟转换逻辑收到放置错误

嗨@ bv.shreeharsha。
您是否可以检查IO包引脚约束是否与BITSLICE上的约束一致，或者BITSLICE是否有约束？
如果顶级IO约束覆盖了SelectIO向导尝试使用的位置，则可能会看到错误。
这是因为BITSLICE上的约束仍然存在，现在与新的IO约束冲突。
如果需要更改IO位置，我将从SelectIO向导自定义GUI执行此操作。



以下为原文

Hi @bv.shreeharsha.
 
Can you check to see if the IO package pin constraints are aligned with the constraint on the BITSLICE, or that the BITSLICE has a constraint?
 
If top-level IO constraints are overriding the locations that the SelectIO Wizard is trying to use, the error might be seen. This would be because a constraint on the BITSLICE still exists, and now conflicts with the new IO constraint. If the IO locations need to be change, I would do this from the SelectIO Wizard customization GUI.

嗨马克，
我按照你的建议做了所有改动。
但它没有成功。
我做了评论顶级包pin限制并运行综合。
我再次发现同样的错误。
请看看并建议我的解决方案。
出现以下错误：为RX选择HP47 bank，为TX选择HP70。
封装引脚是连接的。
[放置30-687]预期的单元格g2ugclk_inst / iserdes / inst / top_inst / bs_top_inst / u_rx_bs / RX_BS [13] .rx_bitslice_if_bs与其关联的I / O一起放置。
请检查单元是否正确连接到任何I / O.
还请检查以确保本机模式下的任何BITSLICE都有位置限制。
[放置30-687]预期的单元格g2ugclk_inst / iserdes / inst / top_inst / bs_top_inst / u_rx_bs / RX_BS [26] .rx_bitslice_if_bs与其关联的I / O一起放置。
请检查单元是否正确连接到任何I / O.
还请检查以确保本机模式下的任何BITSLICE都有位置限制。
谢谢
Shreeharsha
rx_serdes.xdc 4 KB
tx_serdes.xdc 5 KB
syncfpga_ucf.xdc 2 KB
syncfpga_ucf.xdc 2 KB



以下为原文

Hi Marc,
 
I did all changes as you suggested. But it didn't work out. I did comment top level package pin constraints and ran synthesis. Again I found the same error. Kindly have a look and suggest me the solution.
 
Getting the following errors: Selected HP47 bank for RX and HP70 for TX. Package pins are as attched.
 
[Place 30-687] Expected cell g2ugclk_inst/iserdes/inst/top_inst/bs_top_inst/u_rx_bs/RX_BS[13].rx_bitslice_if_bs be placed along with its associated I/O. Please check if the cell is properly connected to any I/O. Please also check to make sure any BITSLICE in native mode has location constraints.
 
[Place 30-687] Expected cell g2ugclk_inst/iserdes/inst/top_inst/bs_top_inst/u_rx_bs/RX_BS[26].rx_bitslice_if_bs be placed along with its associated I/O. Please check if the cell is properly connected to any I/O. Please also check to make sure any BITSLICE in native mode has location constraints.
 
 
Thanks
Shreeharsha
            rx_serdes.xdc ‏4 KB                tx_serdes.xdc ‏5 KB                syncfpga_ucf.xdc ‏2 KB                syncfpga_ucf.xdc ‏2 KB

嗨@ bv.shreeharsha。
查看这些约束文件，我没有找到任何与BITSLICE_RX_TX站点相关的“LOC”约束。
这应该是IP提供的限制因素。
您可以检查生成的输出产品以确保存在这样的约束吗？
如果没有，您可以发送此IP的XCI文件吗？



以下为原文

Hi @bv.shreeharsha. Looking these constraints files, I did not find any "LOC" constraints related to a BITSLICE_RX_TX site. This should be in the constraints that the IP supplies. Can you check the generated output product to make sure such constraints exist?
 
If not, can you send the XCI file for this IP?