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[问答] kc705与iostandard冲突
436 xilinx 连接器 串行
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嗨,大家好,
这就是我的设计。
我正在尝试通过kc705评估板上的FMC HPC连接器发送串行数据。
作为输入,我从4个DIP开关+4个按钮读取8位。
然后序列化数据并发送出去......只需使用此连接器和为FPGA设计的一般结构
[DRC 23-20]规则违规(NSTD-1)未指定的I / O标准 -  22个逻辑端口中的1个使用I / O标准(IOSTANDARD)值'DEFAULT',而不是用户指定的特定值。
这可能导致I / O争用或与电路电源或连接不兼容,从而影响性能,信号完整性或在极端情况下导致设备或其所连接的组件受损。
要更正此违规,请指定所有I / O标准。
除非所有逻辑端口都定义了用户指定的I / O标准值,否则此设计将无法生成比特流。
要允许使用未指定的I / O标准值创建比特流(不推荐),请使用以下命令:set_property SEVERITY {Warning} [get_drc_checks NSTD-1]。
注意:使用Vivado运行基础结构(例如,launch_runs Tcl命令)时,将此命令添加到.tcl文件,并将该文件添加为执行运行的write_bitstream步骤的预挂钩。
问题端口:clk_out。
据我所知,iostandard电压值存在问题。
然后我写下了我用于设计的银行,简而言之
LED(0-3):Bank 33 HP
LED(4):Bank 13 HR
LED(5-6):Bank 17 HR
LED(7):Bank 18 HR
data_in(0-3):Bank 13 HR
data_in(4):银行18人力资源
data_in(5):Bank 34 HP
data_in(6-7):Bank 33 HP
system_clock:Bank 33 HP
start_view:银行17 HP
stop_view:银行17惠普
data_out:Bank 17 HP
据我所知,人力资源/惠普银行类型存在限制,甚至每家银行都有限制,而LED和系统时钟必须具有相同或相似的标签属性。我在互联网上搜索了与银行的标量属性相关的文件。
即使我发现,到目前为止我还是不明白。
你能解释一下还是纠正constraitn文件?
我会很感激的!
提前致谢
FMC_Trial.vhd 3 KB
constraint.xdc 3 KB

以上来自于谷歌翻译


以下为原文

Hi guys,


This what I have with my design. I'm trying to send serial data through FMC HPC connector on a kc705 evaluation board. As an input I read the 8 bits from 4 dip switch + 4 pushbutton. Then serializing the data and sending out... Just playing with this connector and general structure of making a design for an FPGA

[DRC 23-20] Rule violation (NSTD-1) UnspecIFied I/O Standard - 1 out of 22 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting peRFormance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: clk_out.

What I understand there is something wrong with the iostandard voltage values. Then I wrote down the bank I used for the design, in brief they are

LED(0-3) : Bank 33   HP
LED (4)   : Bank 13   HR
LED(5-6) : Bank 17   HR
LED(7)    : Bank 18   HR

data_in(0-3) : Bank 13   HR
data_in(4)    : Bank 18   HR
data_in(5)    : Bank 34    HP
data_in(6-7) : Bank 33   HP

system_clock : Bank 33  HP

start_view  : Bank 17   HP
stop_view  : Bank 17   HP
data_out    : Bank 17   HP

What I understand is there are limitaitons on HR / HP bank types and even for each bank and LED and system clock must have the same or similar iostandard property. I've searched on the internet for finding a document related to iostandard properties of banks. If even I found, I didn't understand it so far. Could you please make a explanation or just correct the constraitn file?

I'll appreciate it!
Thanks in advance





            FMC_Trial.vhd ‏3 KB                constraint.xdc ‏3 KB
0
2018-11-6 11:37:52   评论 分享淘帖 邀请回答
3个回答
您确定您的约束文件在您的项目中吗?
看看日志。
注意任何早期的消息。
是否有另一个xdc约束文件覆盖了您发布的文件?
Austin Lesea主要工程师Xilinx San Jose

以上来自于谷歌翻译


以下为原文

Are you sure your constraints file is in your project?
 
Look at the log.  Pay attention to any earlier messages.  Is there another xdc constraints file over-riding the one you posted?
Austin Lesea
Principal Engineer
Xilinx San Jose
2018-11-6 11:56:42 评论

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这些工具(正确地)告诉您,您的设计中有一个顶级信号没有应用IOSTANDARD(也不是PACKAGE_PIN)。
这使得工具可以选择任何位置并使用“DEFAULT”IOSTANDARD作为引脚。
DRC将此标记为违规,因为将此设置中的设计放在电路板上通常是不合法的。
您的设计具有端口“clk_out”,在.xdc文件中没有相应的约束...
Avrum

以上来自于谷歌翻译


以下为原文

The tools are telling you (correctly) that there is one top level signal from your design that you have not applied an IOSTANDARD (nor a PACKAGE_PIN) to. This lets the tools choose any location and use the "DEFAULT" IOSTANDARD for the pin. The DRC flags this as an violation, since it is generally not legal to put a design in this configuration on a board.
 
Your design has the port "clk_out" for which there is no corresponding constraints in the .xdc file...
 
Avrum
2018-11-6 12:16:39 评论

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谢谢你的回答。
我解决了这个问题。
我正在考虑一个更复杂的解决方案,但有时候会发生这种情况。
介于两者之间我想问一下当我在kc705上声明系统时钟时发出的警告。
LED和系统时钟都在bank 33上,当我使用master xdc文件信息时,它会出错。
如果他们使用不同的IOstandard,为什么他们在同一个银行,为什么不接受主文件信息(时钟LVDS)?
你可能会看到我使用了“DIFF_SSTL15”并且它有一个警告:
[DRC 23-20]规则违规(PORTPROP-2)selectio_diff_term  - 端口clk_in_n具有无效的DIFF_TERM属性值。
对于目标架构,IOSTANDARD值DIFF_SSTL15不支持片上输入差分匹配。
DIFF_TERM属性值将被忽略。
如果某人给出正确的定义,这将非常有帮助。
提前致谢!

以上来自于谷歌翻译


以下为原文

 
Thank you for the answers. I fixed the problem. I was thinking about a more complicated solution but ok sometimes this happens. 
 
in between I want to ask about a warning i'm having when I declare system clock on kc705. LEDs and system clock are both on bank 33 and when I use master xdc file info it gives error. if they use different IOstandard why they are on the same bank and why don't accept the master file info (LVDS for clock)? You may see that I used  " DIFF_SSTL15 " and it works with a warning:
 
[DRC 23-20] Rule violation (PORTPROP-2) selectio_diff_term - The port clk_in_n has an invalid DIFF_TERM property value. For the target architecture, IOSTANDARD value DIFF_SSTL15 does not support on-chip input differential termination. The DIFF_TERM property value will be ignored.
 
 
If some one give the correct definition this will be very helpful. 
 
Thanks in advance!
 
 
2018-11-6 12:25:43 评论

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