差分信号的输入缓冲器的放置错误

我正在使用Vivado 2014.3，为ZC702开发。
合成通过，实现失败。
错误是：
[放置30-378]输入缓冲区的输入引脚adc_if_v1_0_S00_AXI_inst / i_cf_adc_4c / i_adc_if / g_adc_if [0] .i_adc_if_1 / i_data_ibuf与逻辑常量值的非法连接。
我为每对差分信号得到了两个。
我还得到DRC警告说信号是单端的而不是差分的。
在I / O规划布局中，我可以看到该工具将这些信号视为单端信号。
这是我在XPS中开发的自定义IP。
有几个差分时钟信号和一些差分数据信号进入。我怀疑它希望输入缓冲区位于IP的顶层。
这些输入缓冲区在IP层次结构中以较低级别实例化。
我在XPS中没有遇到这样的错误。
是否可以选择允许缓冲器处于较低电平，并将差分信号从顶部连接为差分，直到需要它们的电平并转换为单端？
或者如何在不对我的IP进行太多更改的情况下修复它？



以下为原文

I am using Vivado 2014.3, developing for the ZC702. Synthesis passes, implementation fails.


The error is:

[Place 30-378] Input pin of input buffer adc_if_v1_0_S00_AXI_inst/i_cf_adc_4c/i_adc_if/g_adc_if[0].i_adc_if_1/i_data_ibuf has an illegal connection to a logic constant value.

I get two of these for every pair of differential signal. I also get DRC warnings saying the signals are single-ended and not differential. In the I/O planning layout, I can see that the tool is treating these signals as single-ended.

This is for a custom IP that I developed in XPS. There is a couple of differential clock signals and some differential data signals coming in. I suspect that it wants the input buffer at the top level of the IP. The input buffers for these are instantiated at lower levels in the IP hierarchy. I did not get such errors in XPS. Is there an option to allow having the buffers at lower levels, and connecting the differential signals from the top as differentials, until the level where they are needed and converted to single ended? Or how do I fix it without making too many changes to my IP?