使用ODDR转发多个时钟是否必须实例化几个ODDR？

是的
2.每个IOB都具有ODDR功能
确保检查具有许多此类接口的信号完整性（驱动器不超过同时切换输出限制 -  SSO）。
Austin Lesea主要工程师Xilinx San Jose
在原帖中查看解决方案



以下为原文

1.  Yes
 
2.  Every IOB has ODDR capability
 
Be sure you check the signal integrity of having many such interfaces (drivers do not exceed simultaneous switching outputs limits - SSO).
Austin Lesea
Principal Engineer
Xilinx San JoseView solution in original post

是的
2.每个IOB都具有ODDR功能
确保检查具有许多此类接口的信号完整性（驱动器不超过同时切换输出限制 -  SSO）。
Austin Lesea主要工程师Xilinx San Jose



以下为原文

1.  Yes
 
2.  Every IOB has ODDR capability
 
Be sure you check the signal integrity of having many such interfaces (drivers do not exceed simultaneous switching outputs limits - SSO).
Austin Lesea
Principal Engineer
Xilinx San Jose

@austin感谢你的回复！
所以我想多个ODDR是要走的路......
你究竟是什么意思：
确保检查具有许多此类接口的信号完整性（驱动器不超过同时切换输出限制 -  SSO）。你的意思是BUFG不应该驱动许多输出引脚吗？干杯



以下为原文

@austin

Thanks for the reply!
 
So I guess that multiple ODDRs is the way to go...
 
What exactly do you mean by the:
 
Be sure you check the signal integrity of having many such interfaces (drivers do not exceed simultaneous switching outputs limits - SSO).

Do you mean that a BUFG shouldn't be driving many output pins?

Cheers

你究竟是什么意思：
确保检查具有许多此类接口的信号完整性（驱动器不超过同时切换输出限制 -  SSO）。
当输出缓冲器进行转换时，它从VCCO轨引出电流或通过驱动晶体管将电流吸收到GND。
这些过渡会产生瞬间的电流尖峰。
如果太多的高驱动输出同时进行转换，这些电流尖峰会组合并导致VCCO（称为“下垂”）或GND（称为“接地反弹”）的瞬间中断。
这些的净效应是输出本身可能比预期的转变慢，甚至相邻的信号也会显示出一些中断（即使它们没有转换）。
这称为“同时开关噪声（SSN）”或“同时切换输出（SSO）”的问题。
在一组I / O中，在我们开始看到损坏之前，可以容忍最大数量的SSO。
这取决于（非常高！）I / O标准，驱动强度和转换速率。
它还取决于信号“同时”切换的方式;
即使两个输出切换之间的1ns偏差也足以使它们不被视为“同时”。
通过在同一时钟上使用IOB触发器，我们有意使信号“尽可能同时”。
当我们驱逐时钟时，我们知道每个时钟在每个时钟周期转换两次。
因此，SSN成为一个问题。
但是，它再次高度依赖于I / O标准 - 例如对于具有16mA驱动和快速转换的LVCMOS33，SSO的最大数量非常小 - 远低于存储体中的引脚数。
但是，在慢转换速率下，您几乎可以同时切换所有引脚，没有任何问题。
Vivado（和ISE）有用于验证SSO的设计规则检查 - 在Vivado中它被称为SSN，在ISE中它被称为WASSO（加权平均SSO）。
一定要查看这些......
Avrum



以下为原文

What exactly do you mean by the:
 
Be sure you check the signal integrity of having many such interfaces (drivers do not exceed simultaneous switching outputs limits - SSO).
 
When an output buffer makes a transition, it draws current from the VCCO rail or sinks current to GND through the drive transistors. These transitions create momentary spikes of current.
 
If too many high-drive outputs make transitions simultaneously, these current spikes can combine and cause a momentary disruption of the VCCO (called "droop") or the GND (called "ground bounce"). The net effect of these is that the outputs themselves may transition slower than expected, or even neighboring signals will show some disruption (even if they aren't transitioning). This is called "Simultaneous Switching Noise (SSN)" or the problems of "Simultaneously Switching Outputs (SSO)".
 
Within a single bank of I/Os there is a maximum number of SSO that can be tolerated before we start seeing corruptions. This depends (very highly!) on I/O standard, drive strength and slew rates. It also depends on how "simultaneous" the signals are switching; even a skew of 1ns between two outputs switching can be enough to make them not be considered "simultaneous".
 
By using the IOB flip-flops on the same clock, we are intentionally making the signals "as simultaneous as possible". When we are driving out clocks, we know that every clock transitions at twice a clock period. Thus SSN becomes a concern. But, again, it depends highly on the I/O standard - for example for LVCMOS33 with 16mA drive and fast transition, the maximum number of SSO is pretty small - well below the number of pins in the bank. However, at slow slew rate, you can pretty much have all pins switch simultaneously with no problems.
 
Vivado (and ISE) have design rule checks for verifying SSO - in Vivado it is called SSN, in ISE it is called WASSO (Weighted Average SSO). Be sure to check these...
 
Avrum