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我试图将ov7670相机与zedboard接口。我已经使用了仓鼠代码。
但是当合成和实现获得大量的关键警告时，忽略是否安全？我的比特流也没有产生它的显示错误。我正在接受我所做的一切。 请帮忙。 hoja.zip 968 KB 以上来自于谷歌翻译 以下为原文 I am trying to interface ov7670 camera with zedboard .I have used hamsters code for that . But while synthesis and implementaion getting large amount of critical warning Is it safe to Ignore?My bitstream is not getting generated its showing error in that also .I am atttaching whatever i have done. Please help. 
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谢谢你的回复。我已经看到了已经做了他们所说的.Bitstream正在生成但是当我正在做程序fpga它正在编程但它没有显示输出
在原帖中查看解决方案 以上来自于谷歌翻译 以下为原文 Thanks for replying.I have seen that already and did what they said .Bitstream is getting generated but when i am doing program fpga It is getting programmed but its not showing output View solution in original post |
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我收到了这些严厉的警告
[Common 17-55]'set_property'需要至少一个对象。 [ “C：/Users/admin/hoja/project_1/project_1.srcs/constrs_1/imports/hoja/zedboard.xdc”：1] 像这样的40警告 [DRC 23-20]规则违规（NSTD-1）未指定的I / O标准 - 46个逻辑端口中的46个使用I / O标准（IOSTANDARD）值'DEFAULT'，而不是用户指定的特定值。 这可能导致I / O争用或与电路板电源或连接不兼容，从而影响性能，信号完整性或在极端情况下导致设备或其所连接的组件受损。 要更正此违规，请指定所有I / O标准。 除非所有逻辑端口都定义了用户指定的I / O标准值，否则此设计将无法生成比特流。 要允许使用未指定的I / O标准值创建比特流（不推荐），请使用以下命令：set_property SEVERITY {Warning} [get_drc_checks NSTD-1]。 注意：使用Vivado运行基础结构（例如，launch_runs Tcl命令）时，将此命令添加到.tcl文件，并将该文件添加为执行运行的write_bitstream步骤的预挂钩。 问题端口：vga_red [3：0]，vga_green [3：0]，vga_blue [3：0]，frame_addr [18：0]，frame_pixel [11：0]，clk25，vga_hsync，vga_vsync。 像这样2。 忽略这个是安全的吗？ 请帮忙 以上来自于谷歌翻译 以下为原文 I am getting these critical warning [Common 17-55] 'set_property' expects at least one object. ["C:/Users/admin/hoja/project_1/project_1.srcs/constrs_1/imports/hoja/zedboard.xdc":1] Like this 40 warning [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 46 out of 46 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: vga_red[3:0], vga_green[3:0], vga_blue[3:0], frame_addr[18:0], frame_pixel[11:0], clk25, vga_hsync, vga_vsync. Like this 2. Is it safe to ignore this? please help |
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@tarinip，
请参阅此AR：https：//www.xilinx.com/support/answers/56354.html 谢谢，Nupur ----------------------------------------------- --------------------------------------------- Google在发布之前提问 。 如果某人的帖子回答了您的问题，请将帖子标记为“接受为解决方案”。 如果你看到一个特别好的和信息丰富的帖子，考虑给它Kudos（点击星标）。 以上来自于谷歌翻译 以下为原文 @tarinip, Please see this AR : https://www.xilinx.com/support/answers/56354.html Thanks, Nupur -------------------------------------------------------------------------------------------- Google your question before posting. If someone's post answers your question, mark the post as answer with "Accept as solution". If you see a particularly good and informative post, consider giving it Kudos (click on the star mark). |
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谢谢你的回复。我已经看到了已经做了他们所说的.Bitstream正在生成但是当我正在做程序fpga它正在编程但它没有显示输出
以上来自于谷歌翻译 以下为原文 Thanks for replying.I have seen that already and did what they said .Bitstream is getting generated but when i am doing program fpga It is getting programmed but its not showing output |
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嗨@tarinip，
知道自己在做什么总是更好。 因此，您应该检查为每个IO分配的正确IO标准，并在xdc文件中定义它。 问候， 弗洛朗 FlorentProduct应用工程师 - Xilinx技术支持EMEA ------------------------------------------ -------------------------------------------------- ----------------------------不要忘记回复，kudo，并接受作为解决方案。 以上来自于谷歌翻译 以下为原文 Hi @tarinip, This is always better to know what you are doing. So you should check what are the correct IO standard to assign for every IO and define it in the xdc file. Regards, Florent Florent Product Application Engineer - Xilinx Technical Support EMEA ------------------------------------------------------------------------------------------------------------------------ Don't forget to reply, kudo, and accept as solution. |
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感谢您的回复。我认为我的xdc文件具有正确的IO标准，可以用IO.Can你可以通过它
zedboard.xdc 4 KB 以上来自于谷歌翻译 以下为原文 Thanks for reply.I think my xdc file has correct IO standard for ever IO.Can you please go through it |
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嗨@tarinip，
如果您可以发送vivado.log文件，它可以提供有关错误的更多信息。 但是，xdc看起来很好 问候， 弗洛朗 FlorentProduct应用工程师 - Xilinx技术支持EMEA ------------------------------------------ -------------------------------------------------- ----------------------------不要忘记回复，kudo，并接受作为解决方案。 以上来自于谷歌翻译 以下为原文 Hi @tarinip, If you could send the vivado.log file it could give more information of what is wrong. But yes the xdc looks fine Regards, Florent Florent Product Application Engineer - Xilinx Technical Support EMEA ------------------------------------------------------------------------------------------------------------------------ Don't forget to reply, kudo, and accept as solution. |
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你好Florent，
谢谢你的回复。我附上了我的日志文件 问候 Tarini log file.txt 21 KB 以上来自于谷歌翻译 以下为原文 Hello Florent, Thanks for replying.I am attaching my log file Regards Tarini |
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嗨@tarinip，
这很奇怪。 看来你的xdc文件没有被读取...你能检查一下vivado中是否有正确的文件（在约束源中，它是标记目标吗？） 问候， 弗洛朗 FlorentProduct应用工程师 - Xilinx技术支持EMEA ------------------------------------------ -------------------------------------------------- ----------------------------不要忘记回复，kudo，并接受作为解决方案。 以上来自于谷歌翻译 以下为原文 Hi @tarinip, That is weird. It seems that your xdc file is not read... Could you check if you have the correct file in vivado (in the constraint sources, is it the one marked target?) Regards, Florent Florent Product Application Engineer - Xilinx Technical Support EMEA ------------------------------------------------------------------------------------------------------------------------ Don't forget to reply, kudo, and accept as solution. |
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你好@弗洛朗
感谢回复。 在生成比特流时，我遇到了以下错误 DRC 23-20]规则违规（NSTD-1）未指定的I / O标准 - 46个逻辑端口中的46个使用I / O标准（IOSTANDARD）值'DEFAULT'，而不是用户指定的特定值。 这可能导致I / O争用或与电路板电源或连接不兼容，从而影响性能，信号完整性或在极端情况下导致设备或其所连接的组件受损。 要更正此违规，请指定所有I / O标准。 除非所有逻辑端口都定义了用户指定的I / O标准值，否则此设计将无法生成比特流。 要允许使用未指定的I / O标准值创建比特流（不推荐），请使用以下命令：set_property SEVERITY {Warning} [get_drc_checks NSTD-1]。 注意：使用Vivado运行基础结构（例如，launch_runs Tcl命令）时，将此命令添加到.tcl文件，并将该文件添加为执行运行的write_bitstream步骤的预挂钩。 问题端口：vga_red [3：0]，vga_green [3：0]，vga_blue [3：0]，frame_addr [18：0]，frame_pixel [11：0]，clk25，vga_hsync，vga_vsync。 像这样2。 正如所建议的那样：http：//www.xilinx.com/support/answers/56354.html 我做了这个部分因为我的综合和实现运行没有错误，尽管他们有严重的错误 3.如果您只需要从现有的已完成的实施运行中生成位文件并暂时忽略那些不受约束的I / O，请使用此解决方案 执行此操作后，Xdc文件不会保留约束目标。 我该怎么办？ 问候 Tarini 以上来自于谷歌翻译 以下为原文 Hello @florent Thanks for replying. While generating the bitstream i was getting following error DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 46 out of 46 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: vga_red[3:0], vga_green[3:0], vga_blue[3:0], frame_addr[18:0], frame_pixel[11:0], clk25, vga_hsync, vga_vsync. Like this 2. as suggested in https://www.xilinx.com/support/answers/56354.html I did this part as my synthesis and implementation were run without error though they had critical errors 3. If you just need to generate the bit file from the existing completed Implementation run and temporarily ignore those unconstrained I/Os, use this solution After doing this Xdc file doesnt remain the constraint target. What should I do? Regards Tarini |
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你好@ florentw
先生，我在这附上整个项目。 你能通过它吗？ 提前致谢 project_1.cache.zip 7721 KB project_1.hw.zip 12 KB project_1.ip_user_files.zip 81 KB project_1.runs.zip 1656 KB 以上来自于谷歌翻译 以下为原文 Hello @florentw Sir, I am attaching the whole project here. Could you please go through it ? Thanks in advance |
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嗨@tarinip，
对不起，我不会通过你的项目。我没有时间。 我试过检查synth_1和impl_1文件夹，没有日志文件...请把日志文件发给我。 问候， 弗洛朗 FlorentProduct应用工程师 - Xilinx技术支持EMEA ------------------------------------------ -------------------------------------------------- ----------------------------不要忘记回复，kudo，并接受作为解决方案。 以上来自于谷歌翻译 以下为原文 Hi @tarinip, No sorry I won't go through your project.I don't have time for that. I have tried to check in the synth_1 and impl_1 folder and there is no log files... Please send me the log files. Regards, Florent Florent Product Application Engineer - Xilinx Technical Support EMEA ------------------------------------------------------------------------------------------------------------------------ Don't forget to reply, kudo, and accept as solution. |
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你好@ florentw
它没有生成日志文件。 请问你呢？ 谢谢 Tarini 以上来自于谷歌翻译 以下为原文 Hello @florentw Its not generating log file. Will jou do? Thanks Tarini |
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嗨@tarinip，
不.jou里面没有错误。 只有命令启动。 否则找到运行vivado的路径（在tcl控制台中为pwd）。 在此文件夹中，您应该有一个vivado.log文件。 问候， 弗洛朗 FlorentProduct应用工程师 - Xilinx技术支持EMEA ------------------------------------------ -------------------------------------------------- ----------------------------不要忘记回复，kudo，并接受作为解决方案。 以上来自于谷歌翻译 以下为原文 Hi @tarinip, No the .jou won't have the error inside. only the commands launched. Else find the path where you are running vivado (pwd in the tcl console). In this folder, you should have a vivado.log file. Regards, Florent Florent Product Application Engineer - Xilinx Technical Support EMEA ------------------------------------------------------------------------------------------------------------------------ Don't forget to reply, kudo, and accept as solution. |
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你好@ florentw
这是日志文件 谢谢 Tarini vivado.log 13 KB 以上来自于谷歌翻译 以下为原文 Hello @florentw Here is the Log file Thanks Tarini |
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你好@tarinip，
感谢您的日志文件。 这只是严重警告没有错误。 我不认为它会影响你的设计。 如果你想删除严重警告你可以评论（在开头添加＃）你提到的xdc文件（F5QMAYQILV7T6TF.xdc）的行（即72,74,75,84,87,90,102） 问候， 弗洛朗 FlorentProduct应用工程师 - Xilinx技术支持EMEA ------------------------------------------ -------------------------------------------------- ----------------------------不要忘记回复，kudo，并接受作为解决方案。 以上来自于谷歌翻译 以下为原文 Hello @tarinip, Thanks for the log file. This are only critical warnings no error. I don't think it will impact your design. If you want to remove the critical warning you can comment (add # at the begining) the line of your xdc file (F5QMAYQILV7T6TF.xdc) mentioned (i.e. 72, 74, 75, 84 , 87 ,90,102) Regards, Florent Florent Product Application Engineer - Xilinx Technical Support EMEA ------------------------------------------------------------------------------------------------------------------------ Don't forget to reply, kudo, and accept as solution. |
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你好@ florentw
我做了你的建议只有5个严重警告，但是当我使用硬件管理器对设备进行编程时，它被编程为蓝色LED指示灯亮，一个红色指示灯亮，但它没有显示监视器上的输出 谢谢 Tarini 以上来自于谷歌翻译 以下为原文 Hello @florentw I did what you suggested there are only 5 critical warning but when i program the device using hardware manager it is getting programmed blue led is on and one red led is on but its not showing the output on monitor Thanks Tarini |
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你好@tarinip，
然后你需要使用模拟，ILA等进行调试...... 根本原因的可能性太多，导致它无法正常工作。 您应该自己设计，从测试模式生成器开始，并尝试在监视器上显示某些内容。 使用OV7670作为输入。 问候， 弗洛朗 FlorentProduct应用工程师 - Xilinx技术支持EMEA ------------------------------------------ -------------------------------------------------- ----------------------------不要忘记回复，kudo，并接受作为解决方案。 以上来自于谷歌翻译 以下为原文 Hello @tarinip, Then you need to debug using simulation, ILA etc... There are too many possibilities of root cause for why it is not working. You should do your own design, starting with a test pattern generator and try to display something on the monitor. The use the OV7670 as input. Regards, Florent Florent Product Application Engineer - Xilinx Technical Support EMEA ------------------------------------------------------------------------------------------------------------------------ Don't forget to reply, kudo, and accept as solution. |
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你好@ florentw
我试过测试模式生成器。它工作。 对于OV7670，它无法正常工作 谢谢 Tarini 以上来自于谷歌翻译 以下为原文 Hello @florentw I tried with test pattern generator .Its working . For OV7670 its not working Thank you Tarini |
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