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嗨,伙计们。我试着运行16位CCP定时器中的一个,每5毫秒产生一个中断,每一个数据表图309和第30.6章定时器,当TMR寄存器下位字匹配PR寄存器的下一个字时,我应该得到一个CCP中断。然而,情况并非如此,它是向后的,当与上一个单词匹配时,中断触发。我也尝试了另一种方式,CCT中断在匹配较低的单词而不是上面的单词时发生了火灾。这是一个漫长的一周,我必须做一些愚蠢的事情。谢谢你们能提供的任何帮助。谢谢。下面是代码:(定义为GPM和GPL)
以上来自于百度翻译 以下为原文 Hi guys. I am trying to run one of the 16 bit CCP timers to generate an interrupt every 5 ms. Per the datasheet figure 30-9 and chapter 30.6 timers, I should get a CCP interrupt when the TMR register lower word matches the lower word of the PR register. However that is not the case, it is backwards, the interrupt fires when there is a match to the upper word. I also tried the other way around and the CCT interrupt fires when matching the lower word not the upper word. It has been a long week and I must be doing something dumb. I appreciate any help you guys can spare. Thank you. Here is the code: (the #define is for a GPM vs a GPL) // PIC32MM0256GPM064 Configuration Bit Settings // FDEVOPT #pragma config SOSCHP = OFF // Secondary Oscillator High Power Enable bit (SOSC oprerates in normal power mode.) #ifdef __32MM0256GPM064__ #pragma config ALTI2C = OFF // Alternate I2C1 Pins Location Enable bit (Primary I2C1 pins are used) #pragma config FUSBIDIO = ON // USBID pin control (USBID pin is controlled by the port function) #pragma config FVBUSIO = ON // VBUS Pin Control (VBUS pin is controlled by port function) #endif #pragma config USERID = 0xFFFF // User ID bits (User ID bits) // FICD #pragma config JTAGEN = OFF // JTAG Enable bit (JTAG is disabled) #ifdef __32MM0256GPM064__ #pragma config ICS = PGx2 // ICE/ICD Communication Channel Selection bits (Communicate on PGEC2/PGED2) #else #pragma config ICS = PGx3 // ICE/ICD Communication Channel Selection bits (Communicate on PGEC1/PGED1) #endif // FPOR #pragma config BOREN = BOR0 // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware; SBOREN bit disabled) #pragma config RETVR = OFF // Retention Voltage Regulator Enable bit (Retention regulator is disabled) #pragma config LPBOREN = OFF // Downside Voltage Protection Enable bit (Low power BOR is disabled) // FWDT #pragma config SWDTPS = PS1048576 // Sleep Mode Watchdog Timer Postscale Selection bits (1:1048576) #pragma config FWDTWINSZ = PS25_0 // Watchdog Timer Window Size bits (Watchdog timer window size is 25%) #pragma config WINDIS = OFF // Windowed Watchdog Timer Disable bit (Watchdog timer is in non-window mode) #pragma config RWDTPS = PS1048576 // Run Mode Watchdog Timer Postscale Selection bits (1:1048576) #pragma config RCLKSEL = LPRC // Run Mode Watchdog Timer Clock Source Selection bits (Clock source is LPRC (same as for sleep mode)) #pragma config FWDTEN = OFF // Watchdog Timer Enable bit (WDT is disabled) // FOSCSEL #pragma config FNOSC = FRCDIV // Oscillator Selection bits (Fast RC oscillator (FRC) with divide-by-N) #pragma config PLLSRC = FRC // System PLL Input Clock Selection bit (FRC oscillator is selected as PLL reference input on device reset) #pragma config SOSCEN = OFF // Secondary Oscillator Enable bit (Secondary oscillator (SOSC) is enabled) #pragma config IESO = OFF // Two Speed Startup Enable bit (Two speed startup is disabled) #pragma config POSCMOD = OFF // Primary Oscillator Selection bit (Primary oscillator is disabled) #pragma config OSCIOFNC = OFF // System Clock on CLKO Pin Enable bit (OSCO pin operates as a normal I/O) #pragma config SOSCSEL = OFF // Secondary Oscillator External Clock Enable bit (Crystal is used (RA4 and RB4 are controlled by SOSC)) #pragma config FCKSM = CSECME // Clock Switching and Fail-Safe Clock Monitor Enable bits (Clock switching is enabled; Fail-safe clock monitor is enabled) // FSEC #pragma config CP = OFF // Code Protection Enable bit (Code protection is disabled) #include #include void enable_intr() { unsigned int val; asm volatile("mfc0 %0,$13" : "=r"(val)); val |= 0x00800000; asm volatile("mtc0 %0,$13" : "+r"(val)); INTCONSET = _INTCON_MVEC_MASK; unsigned int status = 0; asm volatile("ei %0" : "=r"(status)); } void __ISR(_CCP1_VECTOR) _CCP1_VECTOR_Handler(void) { //toggle RB7, 100 Hz square LATBINV = 1 << 7; #ifdef __32MM0256GPM064__ IFS2bits.CCP1IF = 0; #else IFS0bits.CCP1IF = 0; #endif } void main() { //8 MHz FRC, WDT disabled enable_intr(); //port D digital out low ANSELB = 0; TRISB = 0; LATB = 0; //config & enable CCP1 intr #ifdef __32MM0256GPM064__ IPC18bits.CCP1IP = 2; IPC18bits.CCP1IS = 2; IEC2bits.CCP1IE = 1; #else IPC7bits.CCP1IP = 2; IPC7bits.CCP1IS = 2; IEC0bits.CCP1IE = 1; #endif //5ms: 8,000,000 * 0.005 - 1 = 39,999 = 0x9c3f CCP1PR = 0x00009c3f;//lower word, no interrupt??? CCP1PR = 0x9c3f0000;//upper word, interrupt, clean 100 Hz on scope CCP1CON1bits.ON = 1; while (1); } |
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4个回答
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我想我不能在没有权限错误的情况下将链接发送到数据表。再试一次:
以上来自于百度翻译 以下为原文 I guess I cannot post the link to the datasheet without a permission error. Trying again: http://ww1.microchip.com/downloads/en/DeviceDoc/60001381a.pdf |
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看起来你使用的是双16位定时器模式。上半部使用CCP1IF,下半部使用CCT1F,尽管这似乎与PIC32 FRM相矛盾。
以上来自于百度翻译 以下为原文 It looks like you are using dual 16 bit timer mode. The upper half is using CCP1IF, the lower half is using CCT1F, although this seems contradict to the PIC32 FRM... |
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我想我必须根据经验证据来创建我的第一个支持票和代码。粉红:
以上来自于百度翻译 以下为原文 I guess I'll have to create my first support ticket and code based on empirical evidence?! pink: |
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数据表是错误的。从Microchip支持:“家庭参考手册是错误的,将被更新。CCPXTMR的低16位将触发CTCXIF事件,而CCPXTMR的上16位将触发CCPXIF事件。谢谢你指出这一点。
以上来自于百度翻译 以下为原文 The datasheet is wrong. From Microchip support: "The family reference manual is wrong and will be updated. The lower 16 bits of the CCPxTMR will trigger the CCTxIF event and the upper 16 bits of the CCPxTMR will trigger the CCPxIF event. Thanks for pointing this out. " |
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