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[问答] 运行测试平台时的实时功耗功能在哪里?
65 xilinx 功耗
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嗨,
我在Verillog中编写了一个ALU模块,也是ALU运行的一批任务的测试平台。
我想看看运行这些任务的ALU的实时功耗(功率与时间曲线)。
我模拟了测试平台并生成了VCD文件。
我将VCD文件加载到Vivado进行电源报告。
但是,此功率报告仅给出了每个组件的总功耗。
它不会随着时间的推移给出我设计的功耗。
无论如何,当我在测试平台上执行任务时,我能找到ALU设计随时间推移的功能吗?
非常感谢。


以上来自于谷歌翻译


以下为原文

Hi,
I wrote an ALU module in Verillog, and also a testbench of a batch of tasks running by the ALU.
I wanna see the real time power consumption of the ALU for running these tasks (power vs time curve). I simulated the testbench and generated the VCD file. I loaded the VCD file into Vivado for power report.
However, this power report only gives me the total power consumption for each component. It doesn't give the power consumption of my design along time.
Is there anyway I can find the power that my ALU design comsumes along time, when it executing the tasks in the testbench? Thanks a lot.

Joe
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2018-10-18 14:23:40   评论 邀请回答
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什么是FPGA系列?
您可以在较旧的FPGA系列中查看XADC(在6和7系列FPGA中),系统监视器。
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以上来自于谷歌翻译


以下为原文

What is FPGA family?
 
You can look at XADC (In 6 & 7-series FPGA'S), System Monitor in older FPGA families.
 
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Please mark this post as an "Accept as solution" in case if it helped to resolve your query. So that it will help to other forum users to directly refer to the answer.

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2018-10-18 14:31:35 评论

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一种粗略的方法是将VCD文件分成时隙并计算每个部分消耗的功率。
如果您可以将其自动化,则可以将插槽缩小到时钟周期。
- 如果提供的信息有用,请将答案标记为“接受为解决方案”。给予您认为有用且回复的帖子。

以上来自于谷歌翻译


以下为原文

One crude way to do this is to split the VCD file into time slots and calculate power consumed by each section.  If you can automate it, you can make the slots as small as a clock period.- Please mark the Answer as "Accept as solution" if information provided is helpful.
Give Kudos to a post which you think is helpful and reply oriented.
2018-10-18 14:51:04 评论

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