小心补偿PFC级可以提高功率因数并降低总谐波失真

电路

图1  - 输出电压表现出两倍于线路频率的纹波
图1显示了作为时间函数的线电流（黑色迹线）和线电压（蓝色迹线）。
由于PFC功能，它们都是正弦曲线。
因此，提供给负载的功率具有正方形正弦曲线的形状，如红色迹线所示。
现在，如红色虚线所示，输出功率通常是恒定的，并且所提供的功率平均匹配负载需求。
PFC级有一段时间提供比所需更多的功率（见“+”符号区域），输出电容吸收这些过剩的能量。
另一方面，当PFC级提供的功率低于所需功率时（参见“ - ”符号区域），输出电容放电以补偿能量不足，第二阶段就会出现。
因此输出电压（绿色迹线）表现出两倍于线路频率的纹波（欧洲通常为100 Hz，美国为120 Hz）。
这种低频纹波是PFC功能所固有的。
现在，传统的电流整形技术要求控制信号（由调节电路提供）是缓慢变化的信号。
否则，线电流将失真，因为环路将对纹波作出反应。
因此，调节环路必须抑制该纹波，这实际上是通过设置非常低的带宽（在20Hz的范围内）来完成的。
这就是为什么PFC系统本质上是慢速系统的原因。
控制信号仍然没有纹波。
实际上，如图2所示，它通常由类型2补偿器提供，其放大输出电压的一部分与参考之间的误差。
因此，我们可以证明，如图3所示，vcontrol（t）在线频率的两倍处呈现纹波，相对于输出电压纹波，π到3π/ 2相移。
该交流分量导致一些电流失真。
我们的PFC级设计用于绘制以下理想电流：K是常数，Vcontrol是无纹波，缓慢变化的信号。
不幸的是，实际吸收的电流是：其中vcontrol（t）交流分量导致一些失真。
让我们计算实际输入电流：
（1）
很少的操作可能导致以下等式：
（2）
它们表明vcontrol（t）纹波提供了第二个基本分量（方程式（2）的蓝色项），如果vcontrol（t）纹波相对于输出电压纹波相移3π/ 2，则可以同相
。
最重要的是三次谐波分量（红色项），只能通过限制控制信号中vcontrol（t）纹波的相对部分来最小化。
因此，环路应设计成强烈衰减Vcontrol（vcontrol（t）dc值）上的vcontrol（t）纹波比。
图2  -  Type-2补偿
图3  - 控制信号纹波
由此，我们可以推断出：
- 应优化vcontrol（t）相位以避免线电流基波的位移。
实际上，这导致vcontrol（t）在输入电压的顶部达到峰值（将高频极点置于尽可能低的频率）
- 希望以高vcontrol（t）dc值运行以最小化。
在这种程度上，随着线幅度增加而降低PWM增益的前馈技术将有很大帮助。
现在要小心。
前馈包括检测线路幅度并在当前整形电路中注入该信息。
同样，此信号中的任何交流纹波都会导致一些失真，如下面的等式所示：
（3）
哪里：
vFF（t）是前馈信号（通常是输入电压的平均部分）。
是信号阶段
没有什么是完美的！
然后必须小心使用前馈，如果它使用平均输入电压，那么建立这种基于平均值的前馈信号可能更倾向于采用2极方法......

以上来自于谷歌翻译

以下为原文

Figure 1  - The output voltage exhibits a ripple at twice the line frequency

Figure 1 shows the line current (black trace) and the line voltage (blue trace) as a function of time. As a result of the PFC function, both of them are sinusoidal. Thus, the power provided to the load has the shape of a square sinusoid as shown by the red trace. Now, as suggested by the red dashed line, the output power is generally constant and the provided power matches the load demand in average. There are periods of time for which the PFC stage provides more power than needed (see “+” sign area) and the output capacitor absorbs this excess of energy. On the other hand, a second phase follows when the PFC stage supplies less power than necessary (see “-” sign area) and the output capacitor discharges to compensate the lack of energy.  The output voltage consequently (green trace) exhibits a ripple at twice the line frequency (typically 100 Hz in Europe, 120 Hz in US). This low-frequency ripple is inherent to the PFC function.
Now, traditional current shaping techniques require the control signal (provided by the regulation circuitry) to be a slowly-varying signal. If not, the line current will be distorted because the loop will react to the ripple. Hence, the regulation loop must reject this ripple, which is practically done by setting a very low bandwidth (in the range of 20 Hz).  That is why PFC systems are slow systems by essence.
Still the control signal is not ripple free.  Actually, as shown by Figure 2, it is generally provided by a type-2 compensator which amplifies the error between a portion of the output voltage and a reference. Hence, we can show that as sketched by Figure 3, vcontrol(t) exhibits a ripple at twice the line frequency, π to 3π/2 phase-shifted with respect to the output voltage ripple.
This ac component causes some current distortion.
Our PFC stage is designed to draw the following ideal current where K is a constant and Vcontrol a ripple-free, slowly-varying signal. Unfortunately, the real absorbed current is:   where vcontrol(t) ac component causes some distortion.

Let’s compute the actual input current:
(1)

Few manipulations could lead to the following equation:
(2)

They show that the vcontrol(t)ripple provides a second fundamental component (blue term of equation (2)) that can be put in phase if the vcontrol(t)ripple is 3π/2 phase-shifted with respect to the output voltage ripple . There is above all a third hARMonic component (red term) which can only be minimized by limiting the relative part of the vcontrol(t)ripple in the control signal. The loop should hence be designed to strongly attenuate the ratio vcontrol(t)ripple over Vcontrol (vcontrol(t)dc value).

Figure 2 – Type-2 compensation

Figure 3 – Control signal ripple

From this, we can deduce:
- The vcontrol(t)phase should be optimized to avoid displacement of the line current fundamental. Practically, this leads vcontrol(t)to peak at the top of the input voltage (place the high-frequency pole as low a frequency as possible)
- It is desirable to operate with high vcontrol(t)dc values to minimize . To that extent, feedforward techniques that reduce the PWM gain as the line amplitude increases is of great help.
Now be careful. Feedforward consists of sensing the line magnitude and injecting this information within the current shaping circuitry. Again, any ac ripple in this signal will cause some distortion as shown by below equation:
(3)
Where:

vFF(t) is the feedforward signal (typically an averaged portion of the input voltage).
is the signal phase

Nothing is perfect!
Care must then been applied with feedforward as well and if it uses the mean input voltage, a 2-pole approach is probably to be preferred for building this average-based feedforward signal...

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小心补偿PFC级可以提高功率因数并降低总谐波失真

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