标准卡在第4阶段

我只想补充说，关闭多线程并没有什么区别。太多了



以下为原文

I'll just add that turning off multi-threading makes no difference.

Stacey

很多保持时间违规 - 也许有很多必须处理的组合逻辑？
----------------------------是的，我这样做是为了谋生。



以下为原文

Lots of hold-time violations -- perhaps there's a lot of combinatorial logic that has to be handled?
----------------------------Yes, I do this for a living.

当par进入第4阶段时，保持时间违规将在第8阶段的几分钟内得到解决。当它停留在第4阶段时，它会“永久地”停留（我将它隔夜一次看到）。我期望最大量
组合逻辑在两个MIG物理中，正如我在其Verilog中看到的那样。
在其他HDL中没有任何异常;
恰恰相反。



以下为原文

When par advances past Phase 4 the hold time violations are resolved within a couple of minutes around Phase 8.  When it gets stuck at Phase 4, it is stuck "forever" (I left it overnight once to see).

I expect the largest amount of combinational logic is in the two MIG phys, just from what I can see in their Verilog.  There's nothing out of the ordinary in the other HDL; quite the opposite.

此问题可能与您的操作系统有关。
您使用的是Windows还是Linux？
通常PAR会在第一次报告时将第一个中间结果写入磁盘
定时。
由于它在此时仍然存在，因此可能与文件访问有关。
很难说为什么
它有时会工作，而不是其他人，但......
-  Gabor
PS  - 保持时间违规在较新的FPGA系列中很常见，尽管它们应该如此
除非与控制不良的时钟偏差有关，否则很容易解决。
-  Gabor



以下为原文

This problem might be related to your operating system.  Are you using Windows or Linux?
Usually PAR will write the first intermediate result to disk right after the first time it reports the
timing.  Since it is sticking at this point, it might be related to file access.  It's hard to say why
it would work sometimes and not others, though...
 
-- Gabor
 
PS - Hold time violations are quite common in the newer FPGA families, although they should
be easily resolved unless they are related to poorly controlled clock skew.
-- Gabor

“正在更新文件：带有当前完全路由设计的xxx.ncd”。
挂起时永远不会出现消息。
我使用的是Windows 7。



以下为原文

The "Updating file: xxx.ncd with current fully routed design." message never appears when the hang occurs.  I am using Windows 7.

我今天已经失去了4个小时。
任何暗示缓解此问题的提示都将受到赞赏（不包括“运行Linux”）。谢谢，Stacey



以下为原文

I've lost 4 hours to this today.  Any hint to mitigate this issue would be appreciated ("Run Linux" excluded).

Thanks,

Stacey

如果这仍然是一个问题，我建议打开一个网页来调查这是否是一个操作系统问题。



以下为原文

If this is still proving to be an issue, I suggest opening a webcase to investigate if this is an OS issue.
 

我怀疑它是操作系统问题，我发生了完全相同的事情，我在Linux下使用ISE 13.3。
在ISE中完全搞砸了（实际上很多东西）。



以下为原文

i doubt that it is OS issue, i have exactly same thing happening, and im using ISE 13.3 under Linux.
 
something (actually lots of things) is completely screwed up in ISE.

我怀疑它是操作系统问题，我发生了完全相同的事情，我在Linux下使用ISE 13.3。
您假设在ISE 13.3中有一个 - 且只有一个 -  PAR挂起机制。
或者你知道我们其他人不知道的事情吗？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

i doubt that it is OS issue, i have exactly same thing happening, and im using ISE 13.3 under Linux.
 
You are assuming that there is one -- and only one -- PAR hang mechanism in ISE 13.3.  Or do you know something the rest of us do not know?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

嗯，这个问题就是一个问题。
另一个问题是：
当有时某些逻辑之间的某些信号由时间违规报告，并且我修复它，但是删除它添加FF等等。然后我再次运行整个实现，然后PAR继续对该信号再次大喊大叫。
然而，该信号不再存在，无论是在声明还是在代码中。
即使在我选择清理项目文件和重新实现之后，事情仍在继续。
它只在我关闭并重新打开ISE时消失。
我注意到的另一件事是，有时在翻译过程附近，ISE刚刚关闭，或者例如当实施完成时，我想要进行静态计时和复制结果，当我按下复制ISE关闭时。
我注意到还有一两件事，但不记得了。
上面提到的是最常见的。
有人提到PAR由于许多违规而冻结，这是真的。
因此，该问题的解决方法是，在设计中采取小步骤，并尝试更频繁地运行整个实现。
这会降低工作速度......但这就是您必须使用Xilinx工具。
没有更好的选择。
当有很多时间违规和卡住时，这些工具无法处理这种情况。
当发生这种情况时，我继续，禁用所有宽的新多路复用器和大逻辑，再次实现，如果成功，那么我开始启用一个接一个的逻辑，看看是什么原因导致了问题。
这是有效的。



以下为原文

Well, one issue is this one.
 
Another issue is:
When sometimes some signal between some logic reported by timing violation, and i fix it, but removing it adding FFs etc. Then i run the whole implementation again, and then PAR continues yelling about that signal again. however, that signal doesnt exist anymore, neither in declaration nor in a code. That thing goes on even after i choose clean up project files and reimplement. It goes away only when i close and reopen ISE.
 
Another thing i noticed is, sometimes near the translate process the ISE just closes, or for example when implementation completed, and i want to go to static timing and copy results, right when i press copy ISE closes.
 
There were one or two more things i noticed, but cant remember. The ones mentioned above are the most frequent.
 
Someone mentioned that PAR freezes due to many hold violations, thats true.
 
So the workaround to that issue would be, go in small steps in design, and try to run the whole implementation more often. That slows down work...but that is what you have to do with Xilinx tools. no better option. those tools cant handle situation when there are lots of timing violations and stuck.
 
When this happens, i go ahead, disable all wide new muxes and big logic, implement again, if it succeeds then i start enabling one logic after another to see what caused problem.
 
thats what works.

确保未启用SmartGuide，并且在进行大的更改后，通常需要执行清理项目文件...
------------------------------------------“如果它不起作用
模拟，它不会在板上工作。“



以下为原文

Make sure that SmartGuide isn't enabled, and after a big change it is usually worth doing a Cleanup Project Files...

------------------------------------------
"If it don't work in simulation, it won't work on the board."

FWIW，我有数百行Xilinx MIG物理代码（参见我之前的回复），其中包含我项目中的大部分大型组合逻辑。
我无意修改该代码。更不用说没有证据表明这就是Par挂起的原因。
:-)“触摸问题直到问题消失”是一个糟糕的解决方案，但是经常需要将基于Xilinx FPGA的项目保持在接近计划的位置。
:-(



以下为原文

FWIW, I have hundreds of lines of Xilinx MIG phy code (see my earlier reply) that contains most of the large combinational logic in my project. I have no intention of modifying that code.

Not to mention that there's absolutely no evidence that this is why Par is hanging. :-)

"Touch things until the problem goes away" is a lousy fix, but far too often it is what is required to keep Xilinx FPGA based projects somewhere near schedule. :-(

“触摸问题直到问题消失”
我有另一个“修复”，对我来说效果很好：
在采用它之前，让其他人使用最新的ISE版本来处理这些错误。
不幸的是，如果您是最新FPGA系列的早期采用者，您可能会被困在
最新（和最快）的版本。
我通常至少有一个家庭背后的前沿和
倾向于仅使用ISE的偶数主要版本。
我对ISE 12.4非常满意
-  Gabor
-  Gabor



以下为原文

"Touch things until the problem goes away"
 
I have another "fix" that has worked reasonably well for me:
 
Let someone else work the bugs out of the latest ISE version before adopting it.
 
Unfortunately if you are an early adopter of the latest FPGA family, you may be stuck with the
latest (and buggiest) version.  I'm usually at least one family behind the bleeding edge and
tend to use only the even-numbered major releases of ISE.  I'm pretty happy with ISE 12.4
 
-- Gabor
-- Gabor

偶数或非偶数......这些工具不可靠。
我现在已经下载了版本，13.4和？
同样的东西......它现在停留在第5阶段，13.3陷入第3阶段（进展良好！）。
我之前提到的唯一解决方法是：只需要以非常小的增量创建设计，并且在每次修改后实现整个设计，以便更早地捕获设置时间违规，如果您不经常实施设计然后PAR卡住，那将是
很难确定新修改的逻辑的哪个部分导致了问题。
进入版本12有其自身的麻烦，例如Spartan6系列的速度文件不太正确，这也是需要考虑的重要事项。
当然，没有什么是不可能的，但很明显，目前使用Xilinx工具无法有效地实现您的设计。
我认为在这个话题中再没有什么可讨论的了。



以下为原文

Even or non even... thse tools are non reliable.
 
I have downloaded right now even version, 13.4, and? same stuff... it gets now stuck at phase 5, 13.3 got stuck on phase 3 (good progress!).
 
The only workaround as i mentioned before is: just to create design in very small increments, and after every modification implement the whole design, so that to catch setup time violations earlier, if you implement design less often and then PAR stucks, it would be hard to determine which part of newly modified logic caused the problem.
 
 
And going to the version 12 has its own troubles, like for example speed files for Spartan6 families are not quite right, which is also crucial thing to consider.
 
 
Of course nothing is impossible, but it is clear that it is not possible to effectively implement your designs with Xilinx tools these days.
 
i think there is nothing else to discuss within this topic anymore.

建议打开一个webcase。
如果你在这里发布的意图是解决问题
而不仅仅是抱怨Xilinx工具的遗憾状态，我建议这样做。
-  Gabor
-  Gabor



以下为原文

A suggestion was made to open a webcase.  If your intent in posting here was to solve the issue
rather than just complain about the sorry state of Xilinx tools, then I would suggest doing so.
 
-- Gabor
-- Gabor

打开一个webcase，等待2周后得到与我描述的几乎相同的解决方法？
不用了，谢谢。
我最近从其他几个人身上发现的这个问题被证明是非常普遍的，对那些负责软件的人来说不应该是个大新闻。



以下为原文

open a webcase, and wait for 2 weeks to get workaround which would be almost same as i described? no thanks.
 
this issue as i discovered recently from several other people turned out to be pretty common, and should not be a big news to those who are responsible for software.

我遇到了路由软件在第6阶段陷入困境的地方，但这表明我们的设计存在错误。
在做了一些故障排除之后，我们发现路由工具正在尽力满足基于DSP的低延迟乘法模块的时序，同时尝试满足所有其他DSP模块的时序要求。
当我们提出相关乘法块的延迟时，路由工具就能完成。
也许它陷入第4阶段意味着你的设计无法满足时机要求？
它被卡住可能确实意味着什么，虽然你可能需要做一些猜测或故障排除来隔离问题。
也许可以尝试评论设计的各个部分，以了解路由的执行方式。
这可能是隔离导致此问题的块的好方法。
安德鲁



以下为原文

I have come across where the routing software gets stuck in phase 6, but that this signified an error in our design. After doing some troubleshooting, we found that the routing tool was trying its best to meet the timing for a DSP-based multiply block with low latency, while trying to meet timing for all the other DSP blocks. When we raised the latency for the multiply block in question, the routing tool was able to finish. 
 
Maybe its getting stuck in phase 4 signifies that your design is not able to meet timing? Its getting stuck probably does mean something, though you may have to do some guess-work or troubleshooting to isolate the issue. 
 
Maybe try commenting out sections of your design to see how the routing performs. This might be a good way to isolate the blocks that are causing this problem. 
 
 
Andrew

经过一次小的逻辑变化后，我陷入了PAR阶段8。
但这是一个非常草率的变化，我添加了一个新的输入并将其投入到很多地方的组合方程中。
我注册了输入，问题就消失了。



以下为原文

I was getting stuck in PAR phase 8 after a minor logic change. 
 
But it was a pretty sloppy change where I added a new input and threw it into a combinatoria equation that went to alot of places.  I registered the input and the problem went away.