模拟了代码生成了位文件实现到套件中模拟输出没有出现在板上

如果您的设计在仿真中工作但在实际硬件中不起作用，那么可能出现的问题非常有限：
信号完整性问题与设备的输入或输出有关
时间裕度问题
电源问题
异步输入，处理不当
如果您的设计在模拟中工作，而不是在真实硬件上工作，这些区别可能有助于集中注意力。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

If your design works in simulation but doesn't work in actual hardware, there is a very limited set of likely problems at hand:

• signal integrity issues with an input or output from the device
  
• timing margin problem
  
• power supply problem
  
• asynchronous input which isn't handled properly
  

If your design works in simulation, but not on real hardware, these distinctions may help focus your attention.
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

谢谢你的回答......
但是对于2模块输出即将到来的第3模块只有输出不会出现在板上..我写的整个3模块都有单个程序



以下为原文

Thank u for ur answer...
 
But for the 2 module output is coming for the 3 rd module only output is not coming in the board.. i  written the whole 3 modules has single program
 

我的建议仍然存在。
你有没有运行chipcope来调试你的设计？
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

My advice still stands.
 
Have you run chipscope to debug your design?
 
-- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

一些其他基本问题类别： 
-  IO放置不正确或缺失或标准约束 
- 时间约束不正确或缺失 
- 生成锁存器的错误HDL代码 
- 来自综合，MAP和PAR的未审查和未解决的警告消息
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

A few additional basic problem categories:
  - incorrect or missing IO placement or standard constraints
  - incorrect or missing timing constraint
  - incorrect HDL code that generates latches
  - unreviewed and unresolved WARNING messages from synthesis, MAP and PAR
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com

panner224@gmail.com写道：
我模拟了我的代码，并成功生成了位文件..同时实现到套件中..预期的模拟输出不会出现在板上..
除了其他优秀的建议外，您的模拟是否是整个系统的真实模拟？
我的意思是：你有适当的FPGA连接设备型号吗？
或者你只是切换位看看会发生什么？
后者不是模拟。
----------------------------是的，我这样做是为了谋生。



以下为原文

panner224@gmail.com wrote:
I m simulated my code and i succesfully generated the bit file .. while implementing into the kit .. expected simulation output is not coming in the board..  

In addition to the other excellent suggestions, is your simulation a true simulation of the entire system? By this I mean: do you have proper models of the devices to which the FPGA connects? Or are you just toggling bits to see what happens?
 
The latter is not a simulation.
----------------------------Yes, I do this for a living.

我在virtex 4中成功实现了我的设计......



以下为原文

i successfully implemented my design in virtex 4...
 

panner224@gmail.com写道：
我在virtex 4中成功实现了我的设计......
那是什么问题？
----------------------------是的，我这样做是为了谋生。



以下为原文

panner224@gmail.com wrote:
i successfully implemented my design in virtex 4...
 

What was the problem, then?
----------------------------Yes, I do this for a living.