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是否有专业的裸金属程序员可用的标准IDE?实际上,我也通常在RTL级编写ARM汇编程序。
坦率地说,我从来没有遇到一个像PSoC Creator IDE /设计师,我当然不会countanence这样的工具,任何项目的一部分,我参与。 以上来自于百度翻译 以下为原文 Is there a standard IDE available for professional bare metal programmers ? actually I also normally write arm assembler at the RTL level. Frankly I have never encountered an IDE like PSOC creator/desighner and I certainly would not countanence such a tool as part of any project I am involved in. |
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这是非常短视的柏树,大多数硅厂商支持一系列的IDE,不,我的意思是出口你的样板给他们。
以上来自于百度翻译 以下为原文 Thats pretty short sighted of Cypress, most silicon vendors support a range of IDE's and no I dont mean by exporting your boilerplate to them |
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正如你可能看到的,PSoC在市场上已经成功的超过10年了。由于内部部件的复杂性(另一方面是使PSoC如此通用),所以选择了组件的示意性条目和配置对话框。您仍然可以使用创建者IDE来创建示意图,并将一切导出到另一个IDE中,比如Eclipse。在那里,你可以使用你最喜欢的语言,甚至汇编。 BTW:你坚持汇编语言和寄存器设置的原因是什么?IMO的市场时间比使用(纽约)高级语言要多得多。在PSOC5中使用HDL和UDP编程来创建自己的组件的挑战使得编程变得足够有趣。 快乐编码 鲍勃 以上来自于百度翻译 以下为原文 As you might see, PSoCs are successfully on the market for quite more than 10 years. Due to the complexity of the internals (which on the other hand is making PSoCs so versatile) the schematic entry and configuration dialogs for the components were chosen. You still might use the Creator IDE to just create the schematic and export everything into another IDE like eclipse. There you may work with your favorite languge, even assembly. BTW: What is your reason behind insisting in assembly language and register-setting? IMHO the time-to-market will be quite a lot more than using a(ny) high level language. And the challenge creating own components using HDL and program one (or more) of the UDBs within a PSoC5 keeps programming interesting enough. Happy coding Bob |
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鲍伯,把你的回答又首先我希望能够计划自己使用和高密度脂蛋白(UDB的是VHDL或Verilog)。我当然不希望使用任何现成的组件从柏树或其他任何人,否则就是一个UDB点!我也不想创建一个原理图首先我似乎没有使用任何级别的柏树的IDE。
我的意图是要使用这个芯片的实时功率控制,高层次的语言,在这样的环境中,无处没有控制优化和延迟过高。 我争论推向市场的时间,你的评论,一位经验丰富的工程师很快学会正确设置了RTL(不像你)比学习的样板代码API(样板厚(愚蠢的)通用的)。 我已经决定了你的平台的严重限制,我不会使用它。 以上来自于百度翻译 以下为原文 Bob, taking your replies in turn firstly I was expecting to be able to program the UDB's myself using and HDL (either vhdl or verilog). I certainly have no wish to use any ready made components from Cypress or anyone else otherwise what is the point of a UDB! Well as I don't wan't to create a schematic in the first place I seem to have no use for the Cypress IDE at any level. My intention was to use this chip for realtime power-control, high level languages have no place in such environments as there is no control over optimisation and latencies are excessive. I dispute your comment about time to market, for an experienced engineer it is faster to learn a properly set-out RTL (unlike yours) than it does to learn an API for boilerplate code (boilerplate is thick (stupid) general purpose and unbendable). I have decided given the severe limitations of your platform I will not be using it. |
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