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本帖最后由 一只耳朵怪 于 2018-6-21 11:10 编辑
谁有AM335X GPIO2的时钟配置函数void GPIO2Moduleclkconfig(void)?或者告诉我下怎么从GPIO1的时钟中修改,startware里面没有,多谢!!! |
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无论是GPIO123,配置都差不多,大概就是看GPIO在哪一个时钟源下面,一步一步打开就好,下面是GPIO1的配置例程
void GPIO1ModuleClkConfig(void) [ /* Configuring L3 Interface Clocks. */ /* Writing to MODULEMODE field of CM_PER_L3_CLKCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) |= CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE; /* Waiting for MODULEMODE field to reflect the written value. */ while(CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE != (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) & CM_PER_L3_CLKCTRL_MODULEMODE)); /* Writing to MODULEMODE field of CM_PER_L3_INSTR_CLKCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) |= CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE; /* Waiting for MODULEMODE field to reflect the written value. */ while(CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE != (HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) & CM_PER_L3_INSTR_CLKCTRL_MODULEMODE)); /* Writing to CLKTRCTRL field of CM_PER_L3_CLKSTCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) |= CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP; /* Waiting for CLKTRCTRL field to reflect the written value. */ while(CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP != (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) & CM_PER_L3_CLKSTCTRL_CLKTRCTRL)); /* Writing to CLKTRCTRL field of CM_PER_L3S_CLKSTCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) |= CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP; /*Waiting for CLKTRCTRL field to reflect the written value. */ while(CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP != (HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) & CM_PER_L3S_CLKSTCTRL_CLKTRCTRL)); /* Writing to MODULEMODE field in CM_PER_OCPWP_CLKCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_CLKCTRL) |= CM_PER_OCPWP_CLKCTRL_MODULEMODE_ENABLE; /* Waiting for MODULEMODE field to reflect the written value. */ while(CM_PER_OCPWP_CLKCTRL_MODULEMODE_ENABLE != (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_CLKCTRL) & CM_PER_OCPWP_CLKCTRL_MODULEMODE)); /* Writing to CLKTRCTRL field of CM_PER_OCPWP_L3_CLKSTCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) |= CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP; /*Waiting for CLKTRCTRL field to reflect the written value. */ while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP != (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) & CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL)); /* Checking fields for necessary values. */ /* Waiting for IDLEST field in CM_PER_L3_CLKCTRL register to be set to 0x0. */ while((CM_PER_L3_CLKCTRL_IDLEST_FUNC << CM_PER_L3_CLKCTRL_IDLEST_SHIFT)!= (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) & CM_PER_L3_CLKCTRL_IDLEST)); /* ** Waiting for IDLEST field in CM_PER_L3_INSTR_CLKCTRL register to attain the ** desired value. */ while((CM_PER_L3_INSTR_CLKCTRL_IDLEST_FUNC << CM_PER_L3_INSTR_CLKCTRL_IDLEST_SHIFT)!= (HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) & CM_PER_L3_INSTR_CLKCTRL_IDLEST)); /* ** Waiting for CLKACTIVITY_L3_GCLK field in CM_PER_L3_CLKSTCTRL register to ** attain the desired value. */ while(CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK != (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) & CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK)); /* ** Waiting for STBYST bit in CM_PER_OCPWP_CLKCTRL register to attain ** the desired value. */ /* while((CM_PER_OCPWP_CLKCTRL_STBYST_FUNC << CM_PER_OCPWP_CLKCTRL_STBYST_SHIFT) != (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_CLKCTRL) & CM_PER_OCPWP_CLKCTRL_STBYST)); */ /* ** Waiting for IDLEST field in CM_PER_OCPWP_CLKCTRL register to attain the ** desired value. */ while((CM_PER_OCPWP_CLKCTRL_IDLEST_FUNC << CM_PER_OCPWP_CLKCTRL_IDLEST_SHIFT) != (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_CLKCTRL) & CM_PER_OCPWP_CLKCTRL_IDLEST)); /* ** Waiting for CLKACTIVITY_OCPWP_L3_GCLK field in CM_PER_OCPWP_L3_CLKSTCTRL ** register to attain the desired value. */ while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK != (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) & CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK)); /* ** Waiting for CLKACTIVITY_L3S_GCLK field in CM_PER_L3S_CLKSTCTRL register ** to attain the desired value. */ while(CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK != (HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) & CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK)); /* Configuring L4 Interface Clocks. */ /* Writing to MODULEMODE field of CM_PER_L4LS_CLKCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) |= CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE; /* Waiting for MODULEMODE field to reflect the written value. */ while(CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE != (HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) & CM_PER_L4LS_CLKCTRL_MODULEMODE)); /* Writing to CLKTRCTRL field of CM_PER_L4LS_CLKSTCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) |= CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP; /* Waiting for CLKTRCTRL field to reflect the written value. */ while(CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP != (HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) & CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL)); /* Verifying if other configurations are correct. */ /* ** Waiting for IDLEST field in CM_PER_L4LS_CLKCTRL register to attain the ** desired value. */ while((CM_PER_L4LS_CLKCTRL_IDLEST_FUNC << CM_PER_L4LS_CLKCTRL_IDLEST_SHIFT) != (HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) & CM_PER_L4LS_CLKCTRL_IDLEST)); /* ** Waiting for CLKACTIVITY_L4LS_GCLK bit in CM_PER_L4LS_CLKSTCTRL register ** to attain the desired value. */ while(CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK != (HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK)); /* ** Waiting for CLKACTIVITY_OCPWP_L4_GCLK bit in CM_PER_OCPWP_L3_CLKSTCTRL ** register to attain the desired value. */ /* while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK != (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) & CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK)); */ /* Performing configurations for GPIO1 instance. */ /* Writing to MODULEMODE field of CM_PER_GPIO1_CLKCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_GPIO1_CLKCTRL) |= CM_PER_GPIO1_CLKCTRL_MODULEMODE_ENABLE; /* Waiting for MODULEMODE field to reflect the written value. */ while(CM_PER_GPIO1_CLKCTRL_MODULEMODE_ENABLE != (HWREG(SOC_CM_PER_REGS + CM_PER_GPIO1_CLKCTRL) & CM_PER_GPIO1_CLKCTRL_MODULEMODE)); /* ** Writing to OPTFCLKEN_GPIO_1_GDBCLK bit in CM_PER_GPIO1_CLKCTRL ** register. */ HWREG(SOC_CM_PER_REGS + CM_PER_GPIO1_CLKCTRL) |= CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK; /* ** Waiting for OPTFCLKEN_GPIO_1_GDBCLK bit to reflect the desired ** value. */ while(CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK != (HWREG(SOC_CM_PER_REGS + CM_PER_GPIO1_CLKCTRL) & CM_PER_GPIO1_CLKCTRL_OPTFCLKEN_GPIO_1_GDBCLK)); /* ** Waiting for IDLEST field in CM_PER_GPIO1_CLKCTRL register to attain the ** desired value. */ while((CM_PER_GPIO1_CLKCTRL_IDLEST_FUNC << CM_PER_GPIO1_CLKCTRL_IDLEST_SHIFT) != (HWREG(SOC_CM_PER_REGS + CM_PER_GPIO1_CLKCTRL) & CM_PER_GPIO1_CLKCTRL_IDLEST)); /* ** Waiting for CLKACTIVITY_GPIO_1_GDBCLK bit in CM_PER_L4LS_CLKSTCTRL ** register to attain desired value. */ while(CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK != (HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_1_GDBCLK)); ] |
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uuwufydsw 发表于 2018-6-21 07:55 对比GPIO1配置的,好像还是不行,希望搞过的人帮看看,多谢! void GPIO2ModuleClkConfig(void) [ /* Configuring L3 Interface Clocks. */ /* Writing to MODULEMODE field of CM_PER_L3_CLKCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) |= CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE; /* Waiting for MODULEMODE field to reflect the written value. */ while(CM_PER_L3_CLKCTRL_MODULEMODE_ENABLE != (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) & CM_PER_L3_CLKCTRL_MODULEMODE)); /* Writing to MODULEMODE field of CM_PER_L3_INSTR_CLKCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) |= CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE; /* Waiting for MODULEMODE field to reflect the written value. */ while(CM_PER_L3_INSTR_CLKCTRL_MODULEMODE_ENABLE != (HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) & CM_PER_L3_INSTR_CLKCTRL_MODULEMODE)); /* Writing to CLKTRCTRL field of CM_PER_L3_CLKSTCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) |= CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP; /* Waiting for CLKTRCTRL field to reflect the written value. */ while(CM_PER_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP != (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) & CM_PER_L3_CLKSTCTRL_CLKTRCTRL)); /* Writing to CLKTRCTRL field of CM_PER_L3S_CLKSTCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) |= CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP; /*Waiting for CLKTRCTRL field to reflect the written value. */ while(CM_PER_L3S_CLKSTCTRL_CLKTRCTRL_SW_WKUP != (HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) & CM_PER_L3S_CLKSTCTRL_CLKTRCTRL)); /* Writing to MODULEMODE field in CM_PER_OCPWP_CLKCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_CLKCTRL) |= CM_PER_OCPWP_CLKCTRL_MODULEMODE_ENABLE; /* Waiting for MODULEMODE field to reflect the written value. */ while(CM_PER_OCPWP_CLKCTRL_MODULEMODE_ENABLE != (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_CLKCTRL) & CM_PER_OCPWP_CLKCTRL_MODULEMODE)); /* Writing to CLKTRCTRL field of CM_PER_OCPWP_L3_CLKSTCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) |= CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP; /*Waiting for CLKTRCTRL field to reflect the written value. */ while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL_SW_WKUP != (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) & CM_PER_OCPWP_L3_CLKSTCTRL_CLKTRCTRL)); /* Checking fields for necessary values. */ /* Waiting for IDLEST field in CM_PER_L3_CLKCTRL register to be set to 0x0. */ while((CM_PER_L3_CLKCTRL_IDLEST_FUNC << CM_PER_L3_CLKCTRL_IDLEST_SHIFT)!= (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKCTRL) & CM_PER_L3_CLKCTRL_IDLEST)); /* ** Waiting for IDLEST field in CM_PER_L3_INSTR_CLKCTRL register to attain the ** desired value. */ while((CM_PER_L3_INSTR_CLKCTRL_IDLEST_FUNC << CM_PER_L3_INSTR_CLKCTRL_IDLEST_SHIFT)!= (HWREG(SOC_CM_PER_REGS + CM_PER_L3_INSTR_CLKCTRL) & CM_PER_L3_INSTR_CLKCTRL_IDLEST)); /* ** Waiting for CLKACTIVITY_L3_GCLK field in CM_PER_L3_CLKSTCTRL register to ** attain the desired value. */ while(CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK != (HWREG(SOC_CM_PER_REGS + CM_PER_L3_CLKSTCTRL) & CM_PER_L3_CLKSTCTRL_CLKACTIVITY_L3_GCLK)); /* ** Waiting for STBYST bit in CM_PER_OCPWP_CLKCTRL register to attain ** the desired value. */ /* while((CM_PER_OCPWP_CLKCTRL_STBYST_FUNC << CM_PER_OCPWP_CLKCTRL_STBYST_SHIFT) != (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_CLKCTRL) & CM_PER_OCPWP_CLKCTRL_STBYST)); */ /* ** Waiting for IDLEST field in CM_PER_OCPWP_CLKCTRL register to attain the ** desired value. */ while((CM_PER_OCPWP_CLKCTRL_IDLEST_FUNC << CM_PER_OCPWP_CLKCTRL_IDLEST_SHIFT) != (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_CLKCTRL) & CM_PER_OCPWP_CLKCTRL_IDLEST)); /* ** Waiting for CLKACTIVITY_OCPWP_L3_GCLK field in CM_PER_OCPWP_L3_CLKSTCTRL ** register to attain the desired value. */ while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK != (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) & CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L3_GCLK)); /* ** Waiting for CLKACTIVITY_L3S_GCLK field in CM_PER_L3S_CLKSTCTRL register ** to attain the desired value. */ while(CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK != (HWREG(SOC_CM_PER_REGS + CM_PER_L3S_CLKSTCTRL) & CM_PER_L3S_CLKSTCTRL_CLKACTIVITY_L3S_GCLK)); /* Configuring L4 Interface Clocks. */ /* Writing to MODULEMODE field of CM_PER_L4LS_CLKCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) |= CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE; /* Waiting for MODULEMODE field to reflect the written value. */ while(CM_PER_L4LS_CLKCTRL_MODULEMODE_ENABLE != (HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) & CM_PER_L4LS_CLKCTRL_MODULEMODE)); /* Writing to CLKTRCTRL field of CM_PER_L4LS_CLKSTCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) |= CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP; /* Waiting for CLKTRCTRL field to reflect the written value. */ while(CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL_SW_WKUP != (HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) & CM_PER_L4LS_CLKSTCTRL_CLKTRCTRL)); /* Verifying if other configurations are correct. */ /* ** Waiting for IDLEST field in CM_PER_L4LS_CLKCTRL register to attain the ** desired value. */ while((CM_PER_L4LS_CLKCTRL_IDLEST_FUNC << CM_PER_L4LS_CLKCTRL_IDLEST_SHIFT) != (HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKCTRL) & CM_PER_L4LS_CLKCTRL_IDLEST)); /* ** Waiting for CLKACTIVITY_L4LS_GCLK bit in CM_PER_L4LS_CLKSTCTRL register ** to attain the desired value. */ while(CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK != (HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_L4LS_GCLK)); /* ** Waiting for CLKACTIVITY_OCPWP_L4_GCLK bit in CM_PER_OCPWP_L3_CLKSTCTRL ** register to attain the desired value. */ /* while(CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK != (HWREG(SOC_CM_PER_REGS + CM_PER_OCPWP_L3_CLKSTCTRL) & CM_PER_OCPWP_L3_CLKSTCTRL_CLKACTIVITY_OCPWP_L4_GCLK)); */ /* Performing configurations for GPIO2 instance. */ /* Writing to MODULEMODE field of CM_PER_GPIO1_CLKCTRL register. */ HWREG(SOC_CM_PER_REGS + CM_PER_GPIO2_CLKCTRL) |= CM_PER_GPIO2_CLKCTRL_MODULEMODE_ENABLE; /* Waiting for MODULEMODE field to reflect the written value. */ while(CM_PER_GPIO2_CLKCTRL_MODULEMODE_ENABLE != (HWREG(SOC_CM_PER_REGS + CM_PER_GPIO2_CLKCTRL) & CM_PER_GPIO2_CLKCTRL_MODULEMODE)); /* ** Writing to OPTFCLKEN_GPIO_1_GDBCLK bit in CM_PER_GPIO1_CLKCTRL ** register. */ HWREG(SOC_CM_PER_REGS + CM_PER_GPIO2_CLKCTRL) |= CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK; /* ** Waiting for OPTFCLKEN_GPIO_1_GDBCLK bit to reflect the desired ** value. */ while(CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK != (HWREG(SOC_CM_PER_REGS + CM_PER_GPIO2_CLKCTRL) & CM_PER_GPIO2_CLKCTRL_OPTFCLKEN_GPIO_2_GDBCLK)); /* ** Waiting for IDLEST field in CM_PER_GPIO1_CLKCTRL register to attain the ** desired value. */ while((CM_PER_GPIO2_CLKCTRL_IDLEST_FUNC << CM_PER_GPIO2_CLKCTRL_IDLEST_SHIFT) != (HWREG(SOC_CM_PER_REGS + CM_PER_GPIO2_CLKCTRL) & CM_PER_GPIO2_CLKCTRL_IDLEST)); /* ** Waiting for CLKACTIVITY_GPIO_1_GDBCLK bit in CM_PER_L4LS_CLKSTCTRL ** register to attain desired value. */ while(CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_2_GDBCLK != (HWREG(SOC_CM_PER_REGS + CM_PER_L4LS_CLKSTCTRL) & CM_PER_L4LS_CLKSTCTRL_CLKACTIVITY_GPIO_2_GDBCLK)); ] |
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首先GPIO1配置之后,是可以正常工作的么? |
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只有小组成员才能发言,加入小组>>
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