i2c slave没有发送确认位

SCL也需要一个真正的上拉（不是FPGA的内部上拉）。
----------------------------是的，我这样做是为了谋生。



以下为原文

SCL needs a real pullup too (not the FPGA's internal pullup).
----------------------------Yes, I do this for a living.

你的意思是SCL？
SCL是传感器的输入，传感器从不将其驱动为低电平。



以下为原文

Do you mean SCL? The SCL is input for the sensor and the sensor never drives it LOW.

如果SCL只是传感器的输入，那么您需要主动驱动它。
你的
scl_io的使用似乎意味着双向三态信号。
如果你做了
而不是FPGA的SCL引脚输出，那么你就不需要电阻了。
-  Gabor



以下为原文

If SCL is only an input to the sensor, then you need to drive it actively.  Your
usage of scl_io seems to imply a bidirectional tristate signal.  If you make the
SCL pin of the FPGA an output instead, then you don't need the resistor.
-- Gabor

yuhui写道：
你的意思是SCL？
SCL是传感器的输入，传感器从不将其驱动为低电平。
但是，如果I2C主设备（您的FPGA）遵守I2C规范，则SCL是主设备上的开漏端口，因此需要一个上拉电阻，无论从设备是否保持SCK延迟/延迟/等等。
在ChipScope显示器上看到的可能与引脚上的内容不匹配。
拖出示波器并开始探测。
----------------------------是的，我这样做是为了谋生。



以下为原文

 

yuhui wrote:
Do you mean SCL? The SCL is input for the sensor and the sensor never drives it LOW.

 
But if the I2C master (your FPGA) adheres to the I2C spec, SCL an open-drain port on the master, and as such requires a pull-up resistor, regardless of whether the slave holds SCK down for delay/etc.What you see on the ChipScope display may not match what's on the pins. Drag out your oscilloscope and start probing.
 
----------------------------Yes, I do this for a living.

我已经将SCL更改为传感器的输入而不是io，我在FPGA中提取了两个i2c总线，它没有改变。
我还用示波器探测引脚，信号与落后镜中的信号完全不同。
我已经尝试了自己的程序以及opencore的IP，我真的不知道原因。
我想知道是否有人可以上传经过测试的i2c主核心，这可能会让人感到欣慰。



以下为原文

I've changed the SCL as input for the sensor instead of io, and I pulled up both i2c bus in FPGA, it doesn't change. 
I've also probe the pins with an oscilloscope and the signals are really different from which in chioscopes.
I've tried my own program and also the IP from opencore and I really don't know the reason.  I'm wondering if anyone could upload a tested i2c master core, that could be hightly appreciate.

请原谅我在中间跳......
使用示波器探测I2C接口时，您是否看到以下问题：
信号电平
- 检查驱动电平，上拉R值
-  FPGA驱动信号或I2C从器件驱动时的问题，还是两者兼而有之？
信号时序
- 检查上拉R值
- 检查状态机中与SCL相关的信号时序
-  FPGA驱动或从驱动时？
信号值
- 数字逻辑问题 - 状态机，逻辑驱动状态机等
- 当FPGA驱动或来自从机的意外响应时？
实际范围波形可能会有所帮助。
链接到传感器数据表可能会有所帮助。
你说传感器板上有1.5K上拉R。
对于奴隶来说这是不寻常的。
从机应具有高值（通常为50K）上拉R，仅用于断开时的浮动输入保护。
只有（单个）主机应具有~2K上拉电阻.I2C是多点总线，并且具有低值上拉Rs（每个）的多个从机将成为问题。
也许数据表推荐1.5K上拉R，但传感器本身不包含一个。
以下是配置为驱动双向开漏I2C引脚的IOBUF的示例实例：
IOBUF＃（。DRIVE（6），//指定输出驱动强度.IOSTANDARD（“LVCMOS33”），//指定I / O标准.SLEW（“SLOW”））//指定输出压摆率I2CCsPin2p5（.O
（SDA_in），// FPGA引脚输入缓冲器的输出，连接到结构.IO（Pin_SDA），//缓冲输入端口（直接连接到顶级端口，FPGA引脚）.I（1'b0），//输出
缓冲输入，由FPGA架构驱动.T（SDA_out））;
//输出缓冲器使能，高=输入（hi-Z输出），低=有效驱动器
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

Pardon me for jumping in the middle...
 
When you probe the I2C interface with an oscilloscope, are you seeing problems with:
 
1. signal levels
- check drive levels, pullup R value
- problem when FPGA is driving signals or when I2C slave is driving, or both?
 
2. signal timing
- check pullup R value
- check signal timing in state machine with respect to SCL
- when FPGA driving or when slave driving?
 
3. signal values
- digital logic problem - state machine, logic driving state machine, etc.
- when FPGA driving or unexpected response from slave?
 
Actual scope waveforms might be helpful.
A link to the sensor datasheet might be helpful.
 
You said the sensor has a 1.5K pullup R on board.  This is unusual for a slave.  A slave should have a high value (typically 50K) pullup R onboard, simply for floating input protection when disconnected.  Only the (single) master should have a ~2K pullup R.  I2C is a multi-drop bus, and multiple slaves with low-value pullup Rs (each) would be a problem.  Perhaps the datasheet recommends a 1.5K pullup R, but doesn't include one in the sensor itself.
 
Here is an example instance of an IOBUF configured to drive a bidirectional, open-drain I2C pin:
IOBUF #(
  .DRIVE(6),               // Specify the output drive strength
  .IOSTANDARD("LVCMOS33"), // Specify the I/O standard
  .SLEW("SLOW") )          // Specify the output slew rate
I2CsdaPin2p5 (
  .O  (SDA_in),    // output of FPGA pin input buffer, connects to fabric
  .IO (Pin_SDA),   // Buffer inout port (connect directly to top-level port, FPGA pin)
  .I  (1'b0),      // output buffer input, driven from FPGA fabric.
  .T  (SDA_out) ); // output buffer enable, high=input (hi-Z output), low=active drive
 
- Bob Elkind
SIGNATURE:
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我上传了实际范围波形。
我不太了解示波器中的波形，因为信号与应有的信号完全不同。
从机地址为0x20（包括写入位'0'，16位寄存器地址为0x301A，16位数据为0x0868）
waveform.rar 1194 KB



以下为原文

I've uploaded the Actual scope waveforms. I don't quite understand the waveform in oscilloscope because the signal is quite different from what it should be. The slave address is 0x20(including write bit'0', the 16bits register address is 0x301A and the 16bits data is 0x0868
            waveform.rar ‏1194 KB

我发给你私信 - 鲍勃
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
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以下为原文

I sent you private message - Bob
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2. Search the forums (and search the web) for similar topics.
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4. Do not post a new topic or question on someone else's thread, start a new thread!
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6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
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＃1。
根据波形判断，信号时序或信号电平没有任何问题。
关于* analogue *信号电平，您无后顾之忧。
＃2。
就正确的数字值而言，我无法对波形轨迹做出正面或反面。
这项工作的正确工具是逻辑分析仪。
下一个最好的工具是数字存储示波器。最后，如果生成正确的触发信号，您可以使用模拟示波器，并且您可以生成重复的波形。
您能否确定您认为不正确的交易，并在有趣事件发生时生成触发逻辑信号？
在这一点上，你有多详细描述你认为问题是什么？
请注意我在上一篇文章中提出的问题。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
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以下为原文

#1.  You don't have any problems whatsoever with signal timing or signal levels, judging by the waveforms.  With respect to *analogue* signal levels, you have no worries.
 
#2.  I'm unable to make heads or tails of the waveform traces, with respect to correct digital values.  The correct tool for this job is a logic analyser.  The next best tool is a digital storage scope,  Finally, you can get by with an analogue scope if you generate a proper trigger signal, and you are able to generate a repetitive waveform.
 
Can you determine the transaction which you believe is incorrect, and generate a logic signal for triggering as the interesting event is occurring?
 
How detailed can you be, at this point, in describing what you believe the problem to be?  Please note the questions asked in my previous post.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

yuhui写道：
我上传了实际范围波形。
我不太了解示波器中的波形，因为信号与应有的信号完全不同。
从机地址为0x20（包括写入位'0'，16位寄存器地址为0x301A，16位数据为0x0868）
我不打算打开一些随机的RAR文件，而且我没有你的源代码，但要记住关于I2C的事情是SCL和SDA是开漏信号。
假设缓冲区具有I输入，O输出和T三态控制。
您的内部逻辑不会驱动I输入。
相反，我是坚定的。
如果要在总线上驱动“1”，则将T置为低电平，这会使缓冲器进入高阻态，并允许外部上拉使信号线为1。
（注意，你实际上并没有在这里“驱动”总线。）如果你想要驱动一个'0'，那么你将T驱动为高电平，这将打开输出，由于缓冲输入永久为低电平，因此输出为0。
----------------------------是的，我这样做是为了谋生。



以下为原文

 

yuhui wrote:
I've uploaded the Actual scope waveforms. I don't quite understand the waveform in oscilloscope because the signal is quite different from what it should be. The slave address is 0x20(including write bit'0', the 16bits register address is 0x301A and the 16bits data is 0x0868

I'm not about to open some random RAR file, and I don't have your source code, but the thing to remember about I2C is that SCL and SDA are open-drain signals. Assume that the buffer has an I input, O output and T tristate control. Your internal logic does NOT drive the I input. Instead, I is grounded. When you want to drive a '1' on the bus, you leave T low, which puts the buffer into high-impedance mode and allows the external pullup to make the signal line a '1'. (Note that you're not actually "driving" the bus here.) If you want to drive a '0' then you drive T high, which turns on the output, which drives '0' since the buffer input is permanently low.
 
----------------------------Yes, I do this for a living.

致Bob Elkind，
我的示波器只提供最基本的功能。
然而，重新编程我的i2c设计后，我的波形更好。
如图所示，停止和启动状态位于波形的开头，i2c从地址为0x20。
传输8位数据后跟随非acknoledge位。
我的程序仅在acknoledge位置为无效时（'0'）永久发送i2c消息字节，当我用示波器探测引脚并强制执行低电平有效复位后，几次异步复位（我的设备上没有按钮，所以我
在复位引脚上做了快捷方式来驱动一个复位信号），我得到了重复的i2c信号，但是示波器波形中没有驱动低位，当我试图改变i2c从机地址时，我仍然能够看到
波形（基本上是相同的波形，所以我没有图片），如果我断开图像传感器与FPGA的连接，两个信号都进入了pull0up状态。
这是否意味着acknoledge位被驱动为0，是否还有其他原因？
当存在重复的i2c信号时，chipcope中的状态机值对应于RTL模拟。
我稍后会上传chipcope结果。



以下为原文

To Bob Elkind,
My oscilloscope provides only the most basic functionnalities. However after reprogramming my i2c design I've got better waveform.
As shown in the picture, the stop and start sates located at the beginning of the wave form, the i2c slave address is 0x20. An non-acknoledge bit followed after 8 bit data transfered. My program sended i2c message byte permanently only when the acknoledge bit is deasserted('0'), when I probed the pins with scope and force an active low reset, after several asynchronous reset(I don't have button on the device so I did short-cut on the reset pin to drive a reset signal ), I got repeative i2c signal, however the acknoledge bit was not driven low in the oscilloscope waveform, also when I tried to change i2c slave address, I was still able to see the waveform(which was basically the same waveform so I did't tate picture), if I disconnect the image sensor from FPGA, both the 2 signals went into pull0up state. Does it mean the acknoledge bit was driven to 0, could there be any other reason?
The state machine value in chipscope corresponded as the RTL simulation when there were repeative i2c signals.  I will upload the chipscope result later on.
 
 
 

致bassaman59，
我在设计中使用了三态缓冲器，当sda_o_en为高时，io_sda被驱动为高阻抗'z'，否则变为'0'，而sda_in被分配给io_sda信号。
我将使用IOBUF来查看更多结果。



以下为原文

To bassaman59,
 I used tri-state buffer in my design, when sda_o_en is high, the io_sda is driven to high impedence 'z' otherwise into '0', and the sda_in is assign to io_sda signal. I will use IOBUF to see further results.

关注单个问题是个好主意。
发送I2C从设备地址字节结束时的NAK（而不是ACK）是一个很小的问题。
对于设计调试，这很好。
应该注意的是，根据示波器跟踪，您在发送从地址之前（正确地）发送了STOP条件和START条件。
在数字协议方面，我认为你的设计应该有效。
一些建议：
1.结果是否一致？
您的上一篇文章表明您的结果可能不一致。
如果结果不一致，那么哪些状态或条件似乎有所不同（换句话说，似乎使它始终成功或始终失败）。
2.您是否在目标（从）设备或其他地方进行了探测（这解决了可能的信号完整性问题）。
3.您是否尝试过改变时钟频率，这会影响结果吗？
（例如，您的目标设备在STOP和START条件之间是否有最小延迟要求？）
4.当您通过I2C同时访问设备时，是否检查过从设备电源是否存在噪声，毛刺等。
5.如果在从属设备上引导热风（例如电吹风）或冷喷，这是否会影响结果？
祝你好运，解决问题的第一步是隔离失败。
您的范围跟踪是一个很大的帮助。
- 鲍勃埃尔金德
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
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以下为原文

Focusing on a single problem is a good idea.  The NAK (instead of ACK) at the end of sending the I2C slave address byte is a small, contained problem.  For design debugging, this is good.
 
It should be noted that, per your scope trace, you are (correctly) sending both a STOP condition and a START condition before sending the slave address.
 
In terms of digital protocol, it looks to me like your design should work.
 
Some suggestions:
 
1.  Are the results consistent?  Your last post suggested that maybe your results were not consistent.  If the results were not consistent, what state or conditions seem to make a difference (in other words, what seems to make it consistently succeed or consistently fail).
 
2.  Have you probed at the target (slave) device, or somewhere else (this addresses possible signal integrity issues).
 
3.  Have you tried varying clock frequency, does that affect results?  (for example, does your target device have a minimum delay requirement between STOP and START condition?)
 
4.  Have you checked the slave device power supply for noise, glitches, etc.  while you are simultaneously accessing the device via I2C.
 
5.  If you direct either hot air (e.g. electric hair dryer) or cold spray at the slave device, does that affect results?
 
Good luck, the first step to solving the problem is isolating the failure.  Your scope traces are a big help.
 
- Bob Elkind
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

只有一个明显的观察：
您是否将从机地址验证为0x20为7位数？
即“0100000”
我看到一些软件包含读/写位作为“地址”的LSB
按照这种说法，当您在示波器轨迹上显示时，写入的地址将为0x40，
和0x41用于读取，证明一个字节的左7位中的地址。
对于像PCF8575这样的扩展端口部分，地址“0100000”是典型的
所有地址引脚都连接得很低。
问候，
的Gabor
-  Gabor



以下为原文

Just one obvious observation:
 
Have you verified the slave address as 0x20 as a 7-bit number?  i.e. "0100000"
 
I have seen some software that includes the read/write bit as the LSB of the "address"
In that parlance the address would be 0x40 for write as you show it on the scope trace,
and 0x41 for read, justifying the address in the left 7 bits of a byte.
 
The address "0100000" would be typical for an expansion port part like a PCF8575
with all of its address pins tied low.
 
Regards,
Gabor
-- Gabor

到Gabor，
是的，i2c从机地址是0x20，包括写入位'0'（{7'h10,0}），我上一篇文章中的问题是，当从机地址错误时，acknoledge位被置为无效。
我正在上传我的i2c控制器代码，有人请帮我查一下代码是否正常？
谢谢。
I2C_verilog.v 13 KB



以下为原文

To Gabor,
Yes, the i2c slave address is 0x20 including the write bit'0'   ({7'h10,0}), the problem in my last post was that the acknoledge bit was deasserted eventhough the slave address was wrong.
 
I'm uploading my i2c controller code, anyone please help me to check if the code is OK? Thank you.
            I2C_verilog.v ‏13 KB

对不起，我上周没有时间专注于i2c调试。
今天我再来一次。
现在我从chipcope上传波形。
我意识到我从示波器得到的波形只是FPGA产生的sda输出信号，而不是双向信号。
当我用传感器连接FPGA时，无论发送什么从机地址，sda引脚被传感器拉下并维持在'0'，当没有连接传感器时，sda被defaut转为'1'，这就是为什么
我改变了i2c从站地址，我仍然可以从示波器获得wave。
chipcope的3位数显示了chipcope的结果（1：正确的slave addres 0x20（包括写入位），2：false slave address，3：没有连接传感器。）这里使用三态缓冲器： 
分配SDA =（SDA_OE == 1'b1）？
1'bz：1'b0;
分配SDA_in = SDA;
感谢您的进一步帮助。



以下为原文

Sorry that I didn't have time to focus on the i2c debugging last week. TodayI just start it again.
Now I'm uploading the waveform from chipscope.
What I realize is that the waveform I got from oscilloscope was only the sda output signal generated from FPGA, but not a biderectional signal.
 
when I connected FPGA with sensor, no matter what slave address sended, the sda pin is pulled down by sensor and maintained to '0', when there's no sensor connected, sda was puuled up by defaut to '1', so that's why enventhough I changed i2c slave address, I still could get wavefrom from oscilloscope.
 
The 3 figure of chipscope shows the result of chipscope (1: correct slave addres 0x20(includingwrite  bit), 2:false slave address, 3:no sensor connected. ) Here the tri-state buffer is used :
   assign SDA = (SDA_OE == 1'b1) ? 1'bz : 1'b0 ;
   assign SDA_in = SDA;
Thanks for your further helps.
 
 

那么，范围痕迹是什么？
传感器已连接或传感器未连接？
如果您从来没有*从传感器看到'生命迹象'，也许是时候回到传感器数据表并验证您的电路和地址设置。
如果你仍然死胡同，那么是时候连接一些其他“已知良好”的I2C从设备，以验证问题是否与传感器有关。
找到一些有效的组合，然后一次改变一件事。
签名：新手的自述文件在这里：http：//forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369总结：1。
阅读手册或用户指南。
你读过手册了吗？
你能找到手册吗？2。
搜索论坛（并搜索网页）以寻找类似的主题。
不要在多个论坛上发布相同的问题。
不要在别人的主题上发布新主题或问题，开始新的主题！5。
学生：复制代码与学习设计不同.6“它不起作用”不是一个可以回答的问题。
提供有用的详细信息（请与网页，数据表链接）.7。
您的代码中的评论不需要支付额外费用。
我没有支付论坛帖子的费用。
如果我写一篇好文章，那么我一无所获。



以下为原文

So, what were the scope traces?  Sensor connected or sensor not connected?  If you have *never* seen 'signs of life' from the sensor, perhaps it's time to go back to the sensor datasheet and verify your circuit and address setting.
 
If you still hit a dead end, then it's time to connect some other 'known good' I2C slave, to verify that the the problem does or does not lie with the sensor.  Find some combination that works, and then change one thing at a time.
SIGNATURE:
README for newbies is here: http://forums.xilinx.com/t5/New-Users-Forum/README-first-Help-for-new-users/td-p/219369

Summary:
1. Read the manual or user guide.  Have you read the manual? Can you find the manual?
2. Search the forums (and search the web) for similar topics.
3. Do not post the same question on multiple forums.
4. Do not post a new topic or question on someone else's thread, start a new thread!
5. Students: Copying code is not the same as learning to design.
6 "It does not work" is not a question which can be answered. Provide useful details (with webpage, datasheet links, please).
7. You are not charged extra fees for comments in your code.
8. I am not paid for forum posts.  If I write a good post, then I have been good for nothing.

上面的两个数字是当传感器未连接时传感器连接最后一个数字的结果。
我的意思是，如果传感器电路出现问题，无论接收到哪个从机地址，传感器在连接时都会一直拉下sda？



以下为原文

The upper two figure were result when sensor connected the last figure when sensor not connected.
What I mean was that the sensor pulled down the sda all the time when it is connected no matter what slave address received, should there be problem with sensor circuit?

你用的传感器是什么？
------您是否尝试在Google中输入问题？
如果没有，你应该在发布之前。太多结果？
尝试添加网站：www.xilinx.com



以下为原文

What sensor are you using?
------Have you tried typing your question into Google?  If not you should before posting.
Too many results?  Try adding site:www.xilinx.com