PIC18F65K40 串口发送怎么也不通...

问答对人有帮助，内容完整，我也想知道答案 0

之前做过PIC16的串口，PIC18K20的DEMO软件也看过，然后觉得在K40上面应该不会太困难

谁知道，，，第一次使用PIC18F65K40，用USART5模块...

一个普通的测试发送 用示波器测量没有任何波形，但是while(!TXSTA5bits.TRMT); 在debug却可以通

过......请各位帮帮忙 给点意见...... 硬件上IO口除了上拉电阻没有接任何其他东西.

感谢各位了！！！！！！！！！！！！

// CONFIG1L

#pragma config FEXTOSC = OFF    // External Oscillator mode Selection bits (Oscillator not enabled)

#pragma config RSTOSC = HFINTOSC_64MHZ// Power-up default value for COSC bits (HFINTOSC with HFFRQ = 64 MHz and CDIV = 1:1)

// CONFIG1H

#pragma config CLKOUTEN = OFF   // Clock Out Enable bit (CLKOUT function is disabled)

#pragma config CSWEN = ON       // Clock Switch Enable bit (Writing to NOSC and NDIV is allowed)

#pragma config FCMEN = ON       // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor enabled)

// CONFIG2L

#pragma config MCLRE = INTMCLR  // Master Clear Enable bit (If LVP = 0, MCLR pin function is port defined function; If LVP =1, RG5 pin fuction is MCLR)

#pragma config PWRTE = OFF      // Power-up Timer Enable bit (Power up timer disabled)

#pragma config LPBOREN = OFF    // Low-power BOR enable bit (ULPBOR disabled)

#pragma config BOREN = SBORDIS  // Brown-out Reset Enable bits (Brown-out Reset enabled , SBOREN bit is ignored)

// CONFIG2H

#pragma config BORV = VBOR_2P45 // Brown Out Reset Voltage selection bits (Brown-out Reset Voltage (VBOR) set to 2.45V)

#pragma config ZCD = OFF        // ZCD Disable bit (ZCD disabled. ZCD can be enabled by setting the ZCDSEN bit of ZCDCON)

#pragma config PPS1WAY = ON     // PPSLOCK bit One-Way Set Enable bit (PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle)

#pragma config STVREN = ON      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)

#pragma config DEBUG = OFF      // Debugger Enable bit (Background debugger disabled)

#pragma config XINST = OFF      // Extended Instruction Set Enable bit (Extended Instruction Set and Indexed Addressing Mode disabled)

// CONFIG3L

#pragma config WDTCPS = WDTCPS_31// WDT Period Select bits (Divider ratio 1:65536; software control of WDTPS)

#pragma config WDTE = OFF       // WDT operating mode (WDT Disabled)

// CONFIG3H

#pragma config WDTCWS = WDTCWS_7// WDT Window Select bits (window always open (100%); software control; keyed access not required)

#pragma config WDTCCS = SC      // WDT input clock selector (Software Control)

// CONFIG4L

#pragma config WRT0 = OFF       // Write Protection Block 0 (Block 0 (000800-001FFFh) not write-protected)

#pragma config WRT1 = OFF       // Write Protection Block 1 (Block 1 (002000-003FFFh) not write-protected)

#pragma config WRT2 = OFF       // Write Protection Block 2 (Block 2 (004000-005FFFh) not write-protected)

#pragma config WRT3 = OFF       // Write Protection Block 3 (Block 3 (006000-007FFFh) not write-protected)

// CONFIG4H

#pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-30000Bh) not write-protected)

#pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)

#pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

#pragma config SCANE = ON       // Scanner Enable bit (Scanner module is available for use, SCANMD bit can control the module)

#pragma config LVP = ON         // Low Voltage Programming Enable bit (Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored)

// CONFIG5L

#pragma config CP = OFF         // UserNVM Program Memory Code Protection bit (UserNVM code protection disabled)

#pragma config CPD = OFF        // DataNVM Memory Code Protection bit (DataNVM code protection disabled)

// CONFIG5H

// CONFIG6L

#pragma config EBTR0 = OFF      // Table Read Protection Block 0 (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)

#pragma config EBTR1 = OFF      // Table Read Protection Block 1 (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)

#pragma config EBTR2 = OFF      // Table Read Protection Block 2 (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)

#pragma config EBTR3 = OFF      // Table Read Protection Block 3 (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)

// CONFIG6H

#pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)

void main(void)

{

    PORT_init();

    Open5USART();

    while(1)

    {

        while(!TXSTA5bits.TRMT);

        TX5REG = 0X55;

    }

    return;

}

void PORT_init(void)

{

    ANSELE = 0X00;

    PORTE = 0xFF;

    TRISE = 0x00;

}

void Open5USART(void)

{

  TRISEbits.TRISE2 = 0;

  TRISEbits.TRISE3 = 1;

  RX5PPS = 0X23;

  TX5PPS = 0X22;

  UART5MD = 0;

  TXSTA5bits.CSRC = 0;

  TXSTA5bits.TX9   = 0;

  TXSTA5bits.TXEN = 1;     // Enable transmitter

  TXSTA5bits.SYNC = 0;

  TXSTA5bits.BRGH = 1;

  RCSTA5bits.RX9  = 0;

  RCSTA5bits.CREN = 0;   

  RCSTA5bits.SPEN  = 1;  // Enable receiver

  BAUDCON5bits.BRG16 = 1;

  BAUDCON5bits.SCKP  = 0;

  SP5BRG = 1665; // HFINTOSC with HFFRQ = 64 MHz       9600

  PIE4bits.RC5IE   = 0;  // Interrupt on receipt  

  PIE4bits.TX5IE   = 0;  // Interrupt on transmission

}

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