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[size=18.6667px]有竞争力薪资!团队氛围好!关注个人发展! [size=18.6667px]投递邮箱:nahu@nvidia.com 职位简介:
→EDAtools →Verification →Backend →Power Shanghaipower team is responsible for researching power expenditures and workloadefficiency to identify architectural, micro-architectural strategies for poweroptimization. We want to hire promising talent who can handle project(s)individually/collectively and also add new dimension to the team. Responsibilities:· Create a methodology/algorithm to evaluate power efficiency on high-level(architecture) designs. · Support IP designers using the power flow to do the power scrubbingwork and improve their power efficiency on micro-arch (ASIC) level. · Understand and perform block level and chip-level power analysis. · Communicate/Cooperate with local and abroad teams with power-relatedprojects. · Co-work with power ARCH team/IP team to evaluate new low-power technologiesand improve chip power efficiency. Requirements:· MSEE/MSCS postgraduate. · Experience in ASICdesign/verification, low power knowledge is a strong plus. · Must befamiliar with at least one of the programming languages, C/C++ (preferred), Python,Perl. · Excellent English writing/speaking skills are desired. · Good communication skills. |
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